In section 4.3.11 NVIC register map (p.217) the base address of the main NVIC register block is stated to be 0xE000E100. The Offset to NVIC_ISER0 is then given as 0x100. This would make the address 0xE000E200.
On p. 208, however, the address of NVIC_ISER0 is given (correctly) as 0xE000E100. The other registers follow on from there.
It would therefore appear that the offsets should be corrected p.217.
However, the ARM Cortex-M4 Processor TRM gives a table of NVIC registers (section 6.2.1, p.6-63). There, there exists a register (ICTR) at offset 0x04 from 0xE000E000. So, perhaps that should be considered the base, and the offsets on p.217 would be correct...
