ADC pot conversions not stable in STM32F103RCT6

[Yeswanth]

I am using stm32f103rct6 controller board. I am not getting fixed ADC values for POT. I was used poll for conversion in ADC. Please attach code to get a fixed ADC value or else please address me for how to solve the problem.

[raptorhal2]

A few counts of noise is normal. What variation are you getting?

[AScha.3 · Accepted solution]

Connect a 100nF cer. cap from adc in to GND. (short connection.)

Helping to have a constant value for adc.

[Yeswanth]

It's continuously changing the values. The changing difference is 40 to 50. Like I want to get 2045 then i was getting the values 2013 to 2065.

[raptorhal2]

That is approximately 1%, somewhat high. But probably not a programming problem.

If you have access to an oscilloscope, check the input signal.

[tjaekel]

If you use a mechanical potentiometer with carbon resistor and mechanical mover - it is never really stable, it creates "noise".

Round your ADC value with a certain "delta" (plus/minus) to eliminate the noise.
BTW: even you would try to set the pot exactly at the same position again (never mind how accurate you are) - analog pots can "age" and the resistance is never the same as before (even current through the pot can change the resistance, e.g. how low, even the ambient temperature).

You have to implement an "error margin", a delta, in order to take the value "as the same" (compensate noise and temperature drift). On analog stuff: it never gives you the same value again.

[ONadr.1]

Data instability can also be caused by an unstable reference voltage for ADC, which is usually connected directly to the MCU power supply. This can be verified by periodically measuring the internal reference voltage source. If this measuring is unstable, the problem is in the reference voltage.

[Yeswanth]

When I use 100nF cer. cap it will be Better.

[tjaekel]

Sure, if you solder a 1F capacitor - it will be "rock-solid" (but you would measure just DC voltage).

You are not fixing the root cause (which might be an instable, noisy reference voltage, do you have a cap. on VREF?). Bear in mind: adding a cap on ADC input pin reduces your frequency you would be able to measure.

And: you can add also a "filter" (average) for several ADC samples (also reducing the bandwidth/frequency), instead of a cap.

As other people have pointed out here: your reference voltage, your power supply (VDD, AVDD) might be the main issue. With a large cap you can "smooth" all signals (remove noise), but if it is what you want to do? (just measuring DC at the end)

[AScha.3]

@Yeswanth , thats what we want, it is the "usual" way to have ADC input "clean" of spikes.

@tjaekel , no you dont understand in detail, what its doing, i explain:

1. He has a "pot" as input, so a variable DC-level, he want to get.

2. Input in actual ADC is a switched cap, the sampling cap, for capacitive redistribution ADC type. (we have here.)

3. ADC of this type need a low input impedance, for the sampling time, that is in the micro-second range.

4. Most simple way to get this , is a low impedance cer.cap directly at the ADC input tp ground.

5. As long as you not filter out the voltage change you expect at this input, make this cap BIG (compared to the 8 pF ADC input sampling cap) ; so for higher speed inputs maybe 470pF giving good result.

6. I know this not only from theory , but from a lot of tests (also on ADCs from other than STM cpus); my special interest was , how good is the resolution below the LSB ...! And so at first you have to get to the quality of the conversion, thats given in datasheet , then look, what this adc can do at its limits. Actually i "playing" around with a F303, thats giving acceptable result at 4096 conversion averages (12,003 V with +/- 0,003V "noise" , for example ), but still not what i expect. (I will go to 16000 averages, and look, how to improve). Of course for DC voltage in a 100ms cpature time. For "AC" at high speed input signal, the game is different: high bandwith opamp needs to come as input buffer.