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ADC overrun error. Multiple DMA usage.

mur
Associate III

Hi,

I am using a NUCLEO F334 development board.

I am using the ADC with the DMA. I developed that feature and tested and everything looked alright. I have been developing some more over that and I see that after startup the values are correct but after a few ms the read values are not correct and in the checked cases, above the expected value.

I have seen that changing totally unrelated parts of code affect this issue happening or not. Changing the compiler optimization also affected whether the issue happens or not.

Browsing around I found an article discussing the usage of the volatile keyword on variables tied to hardware, like the DMA buffer and using the volatile keyword in that buffer made it look like it was the solution as adding or removing the change allowed for repeatable tests where the issue was happening or not, and I moved on. A few unrelated changes later, the issue is back. Do you have any suggestion of what should I check or what is the reason?

In addition, find attached the a picture with the ADC object before and after crashing.0693W000000WxBRQA0.png0693W000000WxBHQA0.png

 EDIT:

I kept testing and saw that whenever the ADC error happens, the hadc1 handler has an error code = 2. Which results from the call to HAL_ADC_ErrorCallback(). However

I see that the error is set to 2 after an overrun error. 

/* Set ADC error code to ADC IP internal error */

     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);

I dont know what might be causing this overrun. I found some an old post (https://community.st.com/s/question/0D50X00009XkaVr/f2xx-what-can-cause-an-adc-overrun) of a user describing the ADC usage with the same configuration as me (multimode, triggered by a timer and handling the data with the DMA) with this same error, but he did not post any solution. In another post he posted an article in his website (https://blog.frankvh.com/2012/01/13/stm32f2xx-stm32f4xx-dma-maximum-transactions/) where he interacted with ST support and concluded that the simultaneous use of more than 2 DMA channels was giving trouble... and I'm using 3 (ADC, UART TX, UART RX).

Then my question, is 8 years later than those posts, is there any extra information on the topic or should I just try to use DMA only twice?

  

Best regards.

10 REPLIES 10
mur
Associate III

ST support helped me troubleshoot the issue and it was due to a high DMA usage which was solved by increasing the S/H times of the ADC. In my case I went from 1.5 cycles to 19.5 and that made it.