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ADC output with offset in some unknown region

Zheng Liang
Associate III

We are migrating project from F303 to G473, but the ADC output of G473 confused us with a strange problem, and with same circuit with F303 project below:

0693W00000Lw4aFQAR.jpgsampling time: 66ns

sampling period: 1.16us

voltage range: 1~3V

Vdda / Vref: 3.3V

Here is thre problem curve output from ADC, the range between this two ramping point got a negative offset from original curve:

0693W00000Lw4ZeQAJ.pngramping points detail:

0693W00000Lw4amQAB.png0693W00000Lw4b6QAB.png 

The output from six channels from dual ADC show that the problem presented randomly.

0693W00000Lw4YvQAJ.png 

Although increasing the sampling time could cover the problem, but the sampling period is too long, we think it's not the right solution, since we used almost same sampling time on F303 project and works fine.

So what's the functional difference between F3 and G4 will cause this problem and how we solve this?

2 REPLIES 2
TDK
Guru

Is VDDA/VREF+ stable with sufficient capacitance on the line?

How far away are the sensors and does the behavior change if you alter how the wires between them run?

If you measure a constant voltage which is generated close to the chip (e.g. 1.5V), is the problem present there as well?

If you feel a post has answered your question, please click "Accept as Solution".

Also, read AN5346.

JW