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ADC Conversion time doesn't change when changing the sampling time

Shaheen
Associate II

Hello,

at the moment i try to verify the conversion time of the ADC that is described in the datasheet.

I measure one channel in regular conversion mode without interrupt. 

To calculate the conversion time i used the equation in the datasheet.

Tconversion = tsampletime + ConversionTime

The resolution is fixed with 14bit -> 17 ADC cycles.

ADC clk = 3682540Hz.

 

I toggle a pin after starting the ADC and i toggle the pin again when EOS flag bit is set: 

GPIOA_NS->BSRR |= GPIO_BSRR_BS0;


while((ADC1->ISR & ADC_ISR_EOC) != (ADC_ISR_EOC))
{
}


GPIOA_NS->BSRR |= GPIO_BSRR_BR0;

 

I measured the Conversion time with the ocilloscope.

 

Here are the results ( at the left hand side the measured conversion time and at the right side the calculated):

There is a delay of 6us because of the pin toggling that i have also taken into account for the measurement results!.

TSmpl [cycles]Tsar [cycles]Tconv + PIN Toggle measurement [us]Tconv + PIN Toggle Theory [us]
51711.911.9
61711.912.2
121711.913.8
201716.316
361720.620.4
681729.329.1
39117116116.8
81417233231.6

 

My question is: Why stays the conversion time the same for the first 3 sampling time configurations?

 

 

3 REPLIES 3
Christian N
ST Employee


This post has been escalated to the ST Online Support Team for additional assistance. We'll contact you directly.

AScha.3
Chief III

Hi,

just (you verified most timings perfectly) , did you verify whats in SMPx[2:0]: (Channel x sampling time selection) really is ?

If you feel a post has answered your question, please click "Accept as Solution".

Hi,

i already checked the respective SMP register. Here i set the sample time to 12 ADC Cycles.

SMP4_reg screenshot.PNG

The register is set like expected.

Below are the ADC1 registers after ADC conversion start and after end of conversion (EOC).