About the SWO output clock configuration for STM32H743

[yongjie989]

Hi Expert,

I have an question about the clock config when I would like to printf via the SWO, below is my current config, but I don't know where are needs modify:

Here have two SystemClock_Config function [1] and [2]:

About the [2]: I from the STM32Cube_FW_H7_V1.5.0 find the config, the config can success to printf, I can see the result in SOW viewer.

vvvvvvvvvvvvvvvvvvvvvvvvvv [1] vvvvvvvvvvvvvvvvvvvvvvvvvv

void SystemClock_Config(void)

{

 RCC_OscInitTypeDef RCC_OscInitStruct = {0};

 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};

 /** Supply configuration update enable 

 */

 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);

 /** Configure the main internal regulator output voltage 

 */

 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);

 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}

 /** Initializes the CPU, AHB and APB busses clocks 

 */

 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;

 RCC_OscInitStruct.HSEState = RCC_HSE_ON;

 RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;

 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;

 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

 RCC_OscInitStruct.PLL.PLLM = 2;

 RCC_OscInitStruct.PLL.PLLN = 12;

 RCC_OscInitStruct.PLL.PLLP = 2;

 RCC_OscInitStruct.PLL.PLLQ = 5;

 RCC_OscInitStruct.PLL.PLLR = 2;

 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;

 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;

 RCC_OscInitStruct.PLL.PLLFRACN = 0;

 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

 {

  Error_Handler();

 }

 /** Initializes the CPU, AHB and APB busses clocks 

 */

 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2

               |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;

 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;

 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;

 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;

 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;

 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;

 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;

 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)

 {

  Error_Handler();

 }

 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_USART2

               |RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_UART7

               |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_UART8

               |RCC_PERIPHCLK_SPI4|RCC_PERIPHCLK_SPI3

               |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_SPI2

               |RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_I2C3

               |RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C4;

 PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;

 PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1;

 PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;

 PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;

 PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;

 PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1;

 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)

 {

  Error_Handler();

 }

}

vvvvvvvvvvvvvvvvvvvvvvvvvv [2] vvvvvvvvvvvvvvvvvvvvvvvvvv

void SystemClock_Config(void)

{

  __HAL_RCC_D2SRAM3_CLK_ENABLE();

 RCC_OscInitTypeDef RCC_OscInitStruct = {0};

 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};

 MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);

 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

 while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) 

 {

 }

 __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);

 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

 RCC_OscInitStruct.HSEState = RCC_HSE_ON;

 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;

 RCC_OscInitStruct.CSIState = RCC_CSI_OFF;

 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

 RCC_OscInitStruct.PLL.PLLM = 5;

 RCC_OscInitStruct.PLL.PLLN = 160;

 RCC_OscInitStruct.PLL.PLLP = 2;

 RCC_OscInitStruct.PLL.PLLQ = 4;

 RCC_OscInitStruct.PLL.PLLR = 2;

 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;

 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;

 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

 {

  Error_Handler();

 }

 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2

               |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;

 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;

 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;

 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;

 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;

 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;

 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)

 {

  Error_Handler();

 }

 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2

               |RCC_PERIPHCLK_I2C1;

 PeriphClkInitStruct.PLL2.PLL2M = 5;

 PeriphClkInitStruct.PLL2.PLL2N = 150;

 PeriphClkInitStruct.PLL2.PLL2P = 2;

 PeriphClkInitStruct.PLL2.PLL2Q = 2;

 PeriphClkInitStruct.PLL2.PLL2R = 6;

 PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;

 PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;

 PeriphClkInitStruct.PLL2.PLL2FRACN = 0;

 PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;

 PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;

 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)

 {

  Error_Handler();

 }

 __HAL_RCC_CSI_ENABLE() ;

 __HAL_RCC_SYSCFG_CLK_ENABLE() ;

 HAL_EnableCompensationCell();

}

Thank you!

[Tesla DeLorean]

It is a function of several things. The connect speed of the SWD and the core clock.​ If the interface works in the first case the PC side settings/configuration is correct. Adjust the settings to match core speed for the second case.