A question about the bus architecture of the STM32 microcontroller

[hosseinam1370]

As we know, the Cortex-M3 can be configured with a frequency of 72 MHz, and the AHB bus frequency can also be set to 72 MHz, which is their maximum frequency. Now, the maximum frequency for the APB1 bus can be set to 36 MHz.

Now the question arises: when the CPU wants to communicate and send data via the APB bus to peripheral modules such as TIM2, why doesn't its speed decrease? Does the CPU wait here?

Is there something here that I haven't taken into account?

[Tesla DeLorean · Accepted solution]

Well on the read side it's likely to stall the pipeline, for writes these are deferred via one or more write buffers, and then the pipeline only stalls if those are still active/pending.

Reads will also stall if write buffers are pending, to ensure IN-ORDER completion of LOAD/STORE actions.

The F1 is also constrained by the slowness of the FLASH, and wait states introduced there, where as subsequent designs had wider FLASH prefetch and caching via ART unit in front of the FLASH array.

[Tesla DeLorean]

https://developer.arm.com/documentation/ddi0337/e/Introduction/Execution-pipeline-stages