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STM32H503RBT6 and CubeMX - DAC Clock Setup is inconsistent with the Datasheet

Omgareyouokaydood
Associate II

Hello!

I've been using STM32 uC for a long time, and I decided to try the STM32H503RBT6 microcontroller.

Using the NUCLEO-H503RB I created a brand new project and set up the DAC (without any timers or DMA, just plain simple direct DAC) and nothing else - (config in the picture below).

Omgareyouokaydood_0-1719591816049.png

Using a scope, I noticed a lot of glitches on the generated waveform (a simple 10 steps waveform from 0V to 3.3V). Sometimes it worked as it should, sometimes it didn't work at all, sometimes it worked but the waveform was super random (Oh! And it even changed this behavior if I simply reset the board). I tried to change a lot of settings (except in the clock config tab), but nothing made it work 100% of the time. Only then I decided to try changing the clock settings.

After a day of frustrating debugging, I noticed that the interface of cubeMX seems to be wrong. I checked a hundred times if I chose the correct microcontroller when making the project, etc, but it was configured correctly.

In the picture below, is the configuration that CubeMX shows me when choosing the clock source and the maximum speed allowed to the DAC. It allows me to choose between 6 clock sources and tells me the frequency should be less or equal to 125 MHz when using HCLK. 

Omgareyouokaydood_1-1719585216766.png

However, according to the datasheet, both settings (6 clock choices and <= 125 MHz) are incorrect:

Omgareyouokaydood_2-1719585352233.png

Omgareyouokaydood_3-1719590730939.png

When I created the project, the HCLK option was already selected. However, the "clock speed" box was red, saying I couldn't use anything more then 125 MHz. And that's where the problems started, since I had to change the clock source because I didn't want to lower my HCLK to 125 MHz. And changing the clock source to others not stated in the datasheet caused a lot of problems.

After a day of debugging, I decided to use the HCL clock and ignore the "wrong clock speed warning". Everything worked as it should and flawlessly. However, every time that I generate a new CubeMX code, it warns me that there are errors, and it can cause a LOT of confusion for my future-self or others that open this project.

 

Therefore, my question is: is CubeMX incorrect or am I missing something ?

CubeIDE version used: 1.15.1 (downloaded 2 days ago)

Board Used: NUCLEO-H503RB

 

Thanks

1 ACCEPTED SOLUTION

Accepted Solutions
STTwo-32
ST Employee

Hello @Omgareyouokaydood 

ADC and DAC are sharing same clock source. In case both are used, the clock can't be higher than the Maximum allowed clock frequency for the ADC as shown on the Table 17:

STTwo32_0-1719595602826.png

 

But, if we use only the DAC, User must still be able to select a clock higher than the ADC limit clock. This is a known issue on the CubeMX that has been already reported on the internal ticket 179875 for correction on the coming version of the STM32CubeMX (coming soon).

Best Regards.

STTwo-32

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

4 REPLIES 4
STTwo-32
ST Employee

Hello @Omgareyouokaydood 

ADC and DAC are sharing same clock source. In case both are used, the clock can't be higher than the Maximum allowed clock frequency for the ADC as shown on the Table 17:

STTwo32_0-1719595602826.png

 

But, if we use only the DAC, User must still be able to select a clock higher than the ADC limit clock. This is a known issue on the CubeMX that has been already reported on the internal ticket 179875 for correction on the coming version of the STM32CubeMX (coming soon).

Best Regards.

STTwo-32

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Thanks for the answer!

However, that is a bummer, because I am going to use an ADC as well.

So, I have to questions:

1) Does this mean that I will have to lower HCLK to a maximum of 125 MHz ?

2) When performing a heavy FPU operation, such as calculating a sine wave, which clock is used? Is it always 250 MHz or is it from one of these (picture below) ?

Omgareyouokaydood_0-1719833711953.png

This is my main concern here. I need a very high FPU clock to create arbitrary wave forms using DAC.

And I already noticed that the computations to make such wave forms are heavy.

Therefore if the FPU unit depends on the HCLK, and I have to lower it to make DAC and ADC work, I am screwed 🙂

 

3) After your post, I made a quick test using 250 MHz with ADC and DAC enabled and both seems to be working correctly. I connected an external power supply to the ADC input channel and it is accurate and stable (readings from 0V to 3.3V). And the DAC is also working properly at the same time. What gives ?

 

Any inputs on this?

Thanks!

Hello @Omgareyouokaydood 

1) As you can see on the Datasheet, on our side, we can ensure that the ADC will work fine only if his frequency is under the maximum frequency mentioned on the datasheet.

2) The FPU is clocked from the same source the Cortex-M33 which use the FCLK that works on a frequency up to 250 MHz. 

3) As you can see on the first note under the table 17 of the datasheet, the frequency values are specified by design and not tested in production. So, it may work on a frequency more than specified but we can't guarantee this.

Best Regards.

STTwo-32 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Ok!

 

Thanks for the explanation and answering all my questions!