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2019 STM32 Wish List

Amel NASRI
ST Employee

Dear Community Members & STM32 fans,

Let’s end 2018 thanking you for your involvement in our Community and wishing you all the best for 2019!

0690X000006CwKbQAK.jpg

As already done in 2017 (https://community.st.com/s/feed/0D50X00009bLPmvSAG) and in 2018 (https://community.st.com/s/feed/0D50X00009bLSAKSA4), we open this space to hear from you.

This is an opportunity for us to evaluate what we deliver as offer and to know your expectations.

If we come back to the STM32 portfolio end of last year, it was like this:

0690X000006CwKgQAK.png

Now the image is getting larger with new products as well as ecosystem components:

0690X000006CwKlQAK.jpg

Compared to the wishes you shared previous years, we weren’t able to answer all proposals for sure, but may be some of our solutions met what you looked for. Like for example: delivering .ioc file in the STM32Cube package which we started with STM32G0...

Either you are a follower of the STM32 history as well as the Community updates, or a new member in this space, would you mind share with us your feedback answering the following 3 questions:

  • What shouldn’t be done (don’t say migration to new Community platform or new CubeMX interface (because both of them will be improved)?
  • What you appreciate the most as STM32 related offer?
  • What do you expect/suggest related to the STM32 and its ecosystem?

All together, keep UP our STM32 Community!

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

171 REPLIES 171
Uwe Bonnes
Principal III

Provide QFN with wettable flank to allow optical inspection.

Regarding 4): What is wrong with the uart idle interrupt?

Uwe Bonnes
Principal III

Allow 1 bit SPI transfer, so that SPI can easily do JTAG and set TMS for the last SCLK.

Uwe Bonnes
Principal III

Allow 1 bit SPI transfer, so that SPI can easily do JTAG and set TMS for the last SCLK.

About SPI: a baud rate register that allows you to configure any frequency instead of a few preset frequencies.

I'd be interested in knowing the staffing levels at Atollic during the last 18-24 months and whether there has been a significant loss in institutional knowledge, especially with key players moving on.

What's ST plan for Atollic, and to retain talent in 2019? There's presumably an integration/synergy play with CubeMX, GFX, etc, but still a lot of people really don't care for Eclipse/Workspaces, or the cargo-cult type button pushing approach to "writing" software.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

I think the battle against boot-leg ST-LINK, J-LINK and U-LINK devices is pretty well lost.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

+1

Asantos
Senior

STM32Cube_FW_XX projects examples made using STM32CubeMx.

More Applications notes showing how to configure the peripherals at register level. Ex

...

 TIM2->CCMR1 = 0x31;  //ICF1 = 3 (FILTER N=8) CC1S = 01b Modo capture 1 (directed TI1-> IC1)

  TIM2->CCER = 0x0A;  //CC1NP =1, CC1P = 1 (both edges)

 TIM2->SMCR = 0x54;  //SMS = 4 (RESET), TS= 5 (trigger by TI1FP1)

...

For example it can't be set to an arbitrary time. There are applications where intracharacter delay may be longer than a character's time, and packets are separated by a defined much longer time. There was such requirement on this forum already.

This (and perhaps some other UART- and SPI-related requests, e.g. smart framing signal) could be better and cheaper handled by an inter-module link to timer. Similar link in the other direction could handle baudrates. This all requires thinking and real-world experience from the designers, and better documentation skills, though.

JW