2 PWM outputs - is this possible?

mxo · ‎2023-09-04

now I'm about to try 2 PWM outputs on STM32G4, one is 1/2 time-base delayed from another one.

I think that it is difficult with using only 1 timer, and if using 2, is it possible?

maybe like following..

using TIM2 & TIM3 for example, both are PWM generate mode (up/down counter)

master = TIM2, slave = TIM3, TIM3 start at TIM2 counter overflow

I'm glad to hear someone can advise me.
Regards.

Sarra.S · ‎2023-09-05

Hello @mxo ,

>>using TIM2 & TIM3 for example, both are PWM generate mode (up/down counter)

You are right, you can use timer synchronization between a master timer and a slave timer! Basically, the first timer will generate a PWM signal and when the counter reaches Time-base/2, its OC signal will become high, at this point, the ITR signal will be issued and the second timer will start counting from this value.

You'll need to check Table 276-TIMx internal trigger connection in the reference manual for the timers' choice.

This video will give a better understanding of the internal triggering system with a demo

Also, check paragraph 29.4.23-Timer synchronization in the reference manual for more details.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

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Issamos · ‎2023-09-05

Hello @mxo

you can generate 2 PWM signals using the same TIMER (TIM2 for exemple) or different TIMERS. Every PWM channel in a TIMER is selected separately.

You have to do the same configuration for both channels and start the generation of the 2 PWMs. The first start at T=0 and the second start at T=TS/2 ( delayed by half signal period).

Best regards.

II

Sarra.S · ‎2023-09-05

Hello @mxo ,

>>using TIM2 & TIM3 for example, both are PWM generate mode (up/down counter)

You are right, you can use timer synchronization between a master timer and a slave timer! Basically, the first timer will generate a PWM signal and when the counter reaches Time-base/2, its OC signal will become high, at this point, the ITR signal will be issued and the second timer will start counting from this value.

You'll need to check Table 276-TIMx internal trigger connection in the reference manual for the timers' choice.

This video will give a better understanding of the internal triggering system with a demo

Also, check paragraph 29.4.23-Timer synchronization in the reference manual for more details.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

mxo · ‎2023-09-05

hello, @Sarra.S

thank you for your advice and big help.

1 more question for my understandings..

>> ..when the counter reaches Time-base/2, its OC signal will become high, at this point, the ITR signal will be issued..

above, you mentioned "OC signal" means Trigger Event "Compare Pulse (OC1)", right?

and, is OC1 only encount when counter overflow, or both overflow & underflow?

tutorial video shows the way that using compare match, but I think it's better to use OC signal event for my application as you mentioned.

the result looks almost what I want but slave PWM pulse has some slight negation now.

again, thank you, and regards.

mxo · ‎2023-09-05

hello, @Sarra.S

I get progress and I would report & appreciate you that my application works fine.

>>the result looks almost what I want but slave PWM pulse has some slight negation now.

that was slave mode misplaced.
I chose was "reset mode", but now in "trigger mode" and work fine.
(still I don't understand why not "reset mode", though..)

anyway, thank you for your help!