1Mbps manchester encoding

strik kiey · ‎2017-09-22

Posted on September 22, 2017 at 11:34

Hi!

For my system I need to send and receive a 1Mbps Manchester encoded signal do you guys maybe have an idea of how I could accomplish this with the STM32 or maybe there is example software I could use. Or maybe a other way is better, using an FPGA between the chip and the MCU. With this extra step it easier to send a 1Mbps signal i think.

I already thought about bit banging with timers but I am not sure if this is accurate enough with 1Mbps

I would love to hear your ideas and suggestions how I can solve this,

Thanks!

Uwe Bonnes · ‎2017-09-22

Posted on September 22, 2017 at 13:35

Manchester decoding is mentioned with the DFSDM device, at least for H74x

waclawek.jan · ‎2017-09-22

Posted on September 22, 2017 at 14:21

Manchester decoding is mentioned with the DFSDM device, at least for H74x

Yes, but no deserializer follows it, rather, it is fed into the filters. Unless this is exactly what the OP wants, this step blurs the input information.

S/PDIF's underlying transport is Manchester too, but SAI/SPDIF-RX combine-in the higher-level protocol so again if this is not exactly what the OP wants it's unusable.

Timers with DMA and SW pre/post processing may be a way to go, if there's enough processing power or time.

I could visualize also a hybrid solution, mcu-assisted clock-generation and recovery and using SPI for the (de)serialization with a trivial 74xx-class logic glue; but I am not going to think this furter.

I already thought about bit banging with timers but I am not sure if this is accurate enough with 1Mbps.

There's too little input information to judge this. Tell us more.

JW

AVI-crak · ‎2017-09-22

Posted on September 22, 2017 at 16:43

Manchester coding in a unique communication protocol can be done on the basis of SPI and two external logic chips.

You can decode using one external logic chip and an SPI port. For a speed of 1 Mbit / s, you can make software synchronization, even the slowest chip from st can handle this task.

Use the external cheapest and compact chip from ST for a speed of 1 Mbit / s, this can be done faster than on an FPGA chip. Literally in one evening on the breadboard. This is the way to free CPU time on the main chip.

To make a unique communication line without the participation of the processor core and external logic, you can use an FPGA chip, for example the EPM3032A series. In this case, fast synchronization and high speeds are available, which in some cases is the main condition.

Look at how a similar problem is solved by other major manufacturers of home appliances. It is possible that the problem was created by you personally as a result of the wrong direction of development.

strik kiey · ‎2017-09-26

Posted on September 26, 2017 at 11:45

Thanks for your input, I think im going for the external microcontroller that just deals with the 1mbps manchester encode and decode. What is the best way to do this?

Encoding, with 2MHz spi output and convert the bits (0=01) or just with timer interrupts that toggle the output (500ns)?

Decoding, with edge timers?

love to hear your ideas again

AVI-crak · ‎2017-09-26

Posted on September 26, 2017 at 18:29

Appetite grows, already 2mb.

Coding Manchester from spi is possible in the native version. This requires an external clock signal, spi in master mode. The output of the frequency you need can be performed in a dozen ways, the easiest - through the timer. The frequency should be 4 times higher than the symbol rate, intermediate reports are needed to encode the exact intervals. An element in the red circle is exclusive or, for example, CD74AC86M. Counters CD4013E, or analogue in the case you need. To bypass errors you will have to use the modeling environment, or the breadboard (much longer). When encoding to the Manchester, there are no stops when there is no data - zeros are transmitted.

Manchester decoding is much easier.

You have a timer, it needs three comparisons, or two comparisons and one overflow, an external start. On the remaining logic elements, we make the pulse generator of the timer start, we need an external comparison circuit for selecting the pulses, the dependence is the output of the comparison of the timer itself. Also, the timer comparison output is used as a clock for spi. On the remaining external trigger is a counter for 2, the output is used for spi input, control from the timer comparison output. The scheme of electrical inclusion of elements can be created in five versions, it all depends on the external hard logic used. The timer output beyond the overflow limit, or the maximum comparison - the trigger of the program synchronization start.

Synchronization is a separate headache.

This is the reason for using a separate ?, or even an FPGA. Before synchronization, you will have to process each received bit in manual mode - using matrices and state tables. After the synchronization, you need to hit the spi, then everything will be automatic.

The data transfer protocol must use the capabilities of the receive buffer spi: commands and data are of equal length, the packet must have a known number of parcels, synchronization and a checksum in each packet. Using your own protocol is not a good idea, you have already been pioneers, use their experience. So it makes sense to use CAN, in this case, synchronization is easier.

You can make a fully programmed Manchester, in the global network there are ready-made examples on C. It works absolutely on any processor, but takes up all of its time. For a small microscope, this can be a problem at a speed of 1mbit and higher, because it still needs to communicate with a large micron. Examples are searched through googol on open repositories and forums.