1. Data cache disable issue, 2. flash interface (AXI vs. TCM)

[pabian]

1. If the Data cache is disabled to solve dma data coherency, it reduce performance a lot?  I know functions SCB_ClearDCache(), SCB_InvalidateDCache() to solve that issue. But there is a risk that an error message will not occur even if omitted by mistake. And another method using MPU is too difficult in freeRTOS. So I want to disable the data cache as long as it doesn't degrade performance much. Does this cause any other problems?
2. I don't know which flash interface to use, AXI or TCM. Are there any restrictions on having to choose between the two? If not, does it matter which one I use?

[SofLit · Accepted solution]

Hello,

I invite you to read two application notes:

• AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series"
• AN4667 "STM32F7 Series system architecture and performance"

Hope they answer your questions.

[Piranha]

In addition to what SofLit showed...

> If the Data cache is disabled to solve dma data coherency, it reduce performance a lot?

Disabling D-cache on Cortex-M7 approximately halves the CPU performance. But it also significantly depends on usage scenario:

https://alexkalmuk.medium.com/cpu-caches-with-examples-for-arm-cortex-m-2c05a339246e

> And another method using MPU is too difficult in freeRTOS.

One doesn't have to use FreeRTOS-MPU. Just configure the memories with MPU and use the basic FreeRTOS.