0-wait state

[matthiaspfister9]

Posted on May 10, 2012 at 15:19

Hello,

I am evaluating the SMT32F407 and I am wondering how it is possible to execute code from flash with 0-wait state. In the datasheet on page 67 it is described that the number of wait states it 5 at the maximum CPU frequency. It is noted that the ART accelerator is capable of compensating these wait states since there is a 128 bit cache. When using 32-bit instructions, only 4 instructions can be stored, which is not enough to compensate for 5 wait states. Can someone explain me how this is possible? Thanks in advance! #flash #wait-state

[Tesla DeLorean]

Posted on May 10, 2012 at 15:56

The flash has an access time around 30ns, and 128-bit wide as I recall. To run in zero wait state you'd want to run it at 24 MHz or below, it might be able to touch 32 MHz but probably not across process and temperature. So for every 24 MHz increment, add another wait state.

A lot of instructions aren't single cycle, and the processor is pipelined, and prefetches. You'll take a hit if you branch, or load/store. Most of the instructions aren't 32-bit. As I recall ART has a deeper cache than you indicate, perhaps 64x 128-bit cache lines, in a 4-way fashion. I'll look for a cite. Want to run 0-wait state, then copy your critical code into the 64 KB of CCM (Closely Coupled Memory, aka TCM) and run it there.

http://www.st.com/internet/com/SALES_AND_MARKETING_RESOURCES/MARKETING_PRESENTATIONS/PRODUCT_PRESENTATION/stm32f4_marketing_pres.pdf