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STM32G431 + DRV8323H - High-side FETs overlapping despite hardware dead time

shane mattner
Senior

[VERSION]: MCSDK 6.3.1 & 6.3.2
[TOOL]: MCWB, Motor Pilot

Zip file contains MCWB project file and Board Designer file.

I'm having an issue with gate drive timing using:
- MCU: STM32G431RB
- Gate Driver: DRV8323H (Hardware interface version)
- Using STM32 MCWB and Motor Pilot for configuration
- MOSFETs: IAUC45N04S6N070H

Issue:
My scope captures show overlapping high-side FET gate signals despite the DRV8323H's built-in 100ns hardware dead time. The driver is configured in 6x PWM mode (MODE pin to GND) with maximum gate drive current (IDRIVE to 3.3V). The command to start comes from Motor Pilot to do a speed control command. 

Relevant settings:
- PWM frequency: ~16kHz
- Using complementary PWM outputs
- DRV8323H hardware settings:
* MODE = GND (6x PWM mode)
* IDRIVE = 3.3V (1A source/2A sink)

Scope captures show:
1. Multiple high-side gates being driven high simultaneously
2. ~4μs between transitions
3. Full 0-10V gate voltage swing

Has anyone encountered similar issues or have suggestions for proper PWM configuration with this setup? Particularly interested in Motor Pilot settings that might affect phase timing and synchronization.  I tried changing dead times from 1000ns to 0ns

Picture of complete event from command sent to fault

shanemattner_0-1731351435328.png

shanemattner_1-1731351458481.png

 

Initial pwm turn on:

shanemattner_2-1731351475531.png

 

PWM transition from full on/off to pwm-ing:

shanemattner_3-1731351495626.pngshanemattner_4-1731351505377.png

 

shanemattner_5-1731351520372.png

 

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