Oops, forgot to answer your question about "sub-second update mode". By that, I'm referring to the activating the 'addin' register (ETH_PTPSSIR) which when active (bit 1 TSFCU of ETH_PTPTSCR) sets Fine Update (as opposed to Coarse Update). Coarse Update just adjusts the PTP clock every Sync event (via bit 3 TSSTU of ETH_PTPTSCR) and the PTP clock is 'free running', based on the STM32Fx clock, between updates. In Fine Update mode, the PTP clock is also adjusted every Sync event, but instead of it 'free running' until the next update, the addin register (ETH_PTPTSAR) is adjusted to compensate for differences in frequency between the master and slave clocks. The adjusted addin value (ETH_PTPTSAR) is added to an internal 32 bit PTP accumulator register every uP clock. When that accumulator rolls over, it increments the subsecond PTP register (ETH_PTPTSLR) by a fixed amount (ETH_PTPSSIR).
You can also specify whether one second, the subsecond part of the PTP timer (ETH_PTPTSLR), is represented by 2^31 or 10^9. This is set by bit 9 TSSSR of ETH_PTPTSCR. IEEE-1588 uses (and PTP aware switches) use 10^9, but that requires extra processing to handle in typical code. Because I wasn't directly implementing IEEE-1588, I selected 2^31 mode since it make the math easier. My calculations using t1, t2, t3, and t4 just use the subsecond portion of the PTP timer (since the Sync pulses happen well under a second) and shift it left 1 bit and treat it like a signed value. That shift is done when t1, t2, t3 and t4 are sampled.
Hope that helps.
