Where are all the hardware register addresses defined?

[JoniS]

Hi, the title pretty much says what i'm after.

Used CubeMx to generate the startup code and hardware inits to get fast start.

Sure the periephals works and got the micro running, but i want to get bit closer to hardware and decided to start from Can RX interrupt, just cant figure where or how most of the registers are defined or am i expecting too much when i think those should be defined by default with same names as in datasheet.

the MCU in question is STM32F446RE if that matters, and i'm using VISUALGDB

EDIT: or do i need to do it like -> "#define CAN_RI0R (CAN_BASE) + (offset from datasheet)" since there is no definition for it by default?

[S.Ma]

For STM32L4R5, there are 2 files to look for:

stm32l4r5xx.h

Get familiar with "find in files" menu option in your IDE to dig through the project files.

[JoniS]

thx, i did look into the corresponding file in my project before to try find what i'm after, looked bit more carefully this time.

it seems that it might found inside "CAN_typeDef" struct as "SFIFOMailBox" struct, atleast they included comment about the address offset in there, since the naming is r*******d, it should have been CAN_RIxR obviously as in datasheet.

[waclawek.jan]

Yes, the names are then different, and ST should sync those definitions with the RM; but at least there's a CAN_TypeDef contains *all* the CAN registers. This is not the case for example for the OTG, where the registers are scattered across 4 or 5 types, and ST themselves uses a bunch of macro-based contraptions to access them, rather than fixing this properly.

Unfortunately, the STM32 CMSIS-mandated device headers still leave a lot to be fixed, and ST simply ignores users' comments and requests. It took 10 years until ST added the "xxxPos" definitions for the bit positions within registers, a feature other Cortex-M manufacturers had from start off. So I don't hold my breath.

ST's stance is, that you ought to click in CubeMX and don't ask questions.

JW

#CMSIS_mandated_device_headers

[turboscrew]

Adresses - or rather bases and offsets for peripherals are found in the reference manual, and core peripheral addresses in ARM ARM.

[S.Ma]

Actually physical addresses are a combination of the reference manual respective to a peripheral relative offset and the datasheet for the absolute address.

In IAR, I right click a type or variable or fucntion and "go to definition" will find where something is declared or defined.

[MikeDB]

And if you get compile errors, remember most documentation will usually say something like RCC_D2CCIP2R whereas the libraries only contain RCC->D2CCIP2R

[JoniS]

Yeah that's reasonable, periephal->register should be standard imo, don't know if it's just me, but I find that as best way to declare/define the registers.

Either way was it register prefixed with the periephal or ​x->x, it should be consistent with the reference manual, some of the can registers I wanted to access had just horrible naming convention and it was not obvious at all. If the reference manual talks about RIxR register how one is supposed to know you actually find it under can_typedef->sfifomailbox in the end, I guess it does have something to do with how easy the driver code was write, but that doesn't make it any better.

[MikeDB]

Yes I prefer -> as well, but Atmel do it sensibly and accept either whereas ST programmers have gone solely for the pointer where their documentation team has gone underscore only which does mislead people.

[JoniS]

Atmel have done good job with that yes, I actually did come from their 8bit mcu's to stmf4 series since my current ​project needs way faster processing than what the 8 bitters could do. Atmel doing good job propably was the reason why i expected it to be "standard" in the industry, could have not been more wrong.

Btw, you happen to know if there is any good read about the can hw implementation in the stm32f4 series? Mostly interested in the how the receive fifo works, since it can store 3 messages, but only lets program access to 2 messages via registers, is the third one shifted to first or second slot after the corresponding bit is cleared by software, but I guess that's for another topic.