2024-09-12 11:35 AM - last edited on 2024-09-12 11:43 AM by SofLit
Good afternoon.
I am configuring a NAND memory using FMC on the STM32H7. I am dealing with the following scenario: HCLK = 80 MHz (to match the example in AN4761) and a NAND memory SkyHigh Memory S34ML01G1 Following all the calculations specified in AN4761, I am encountering an error where the last byte fails on some pages. When a read is performed more than once, the byte is corrected, but there is this inconsistency. Where could the error be?
Solved! Go to Solution.
2024-09-13 01:28 AM
Hello @neemiasims,
Which STM32H7 are you using?
Please try to configure the NAND memory area as Strongly-Ordered using MPU, for that I recommend you to take a look at STM32 MPU tips - 1 MPU usage in STM32 with ARM Cortex M7.
Thank you.
Kaouthar
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2024-09-13 01:28 AM
Hello @neemiasims,
Which STM32H7 are you using?
Please try to configure the NAND memory area as Strongly-Ordered using MPU, for that I recommend you to take a look at STM32 MPU tips - 1 MPU usage in STM32 with ARM Cortex M7.
Thank you.
Kaouthar
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2024-09-13 04:22 AM
I am using the STM32H723ZGTx. I am not working with MPU; it was disabled in the 'CORTEX_M7'. I will look into using it to see if it solves the problem. One detail: If I add a 1ms delay after each read and write, the last byte works perfectly, but this makes the memory operation very slow.