The latest RM for STM32L4 I could find mentions the STSPHST bit on page 1702, but makes no mention of how to actually use this bit. Granted, I'm working on a STM32L476 and given table 318, the STSPHST bit is not supported anyways. Nonetheless, I don't find this bit to be defined at all in the CMSIS header file stm32l496xx.h, so what gives? Is this bit deprecated?
The only reason why I'm interested in this bit is because I'm trying to perform a control write transfer on the device side. I got to the point where I'm decoding the SETUP request of SET_LINE_CODING for CDC, configuring the default OUT endpoint to receive a single packet, waiting for RXFLVL, popping off the packet status using GRXSTSP, reading in the RX-FIFO data, and then finally popping off the "OUT transfer completed" status word pattern.
The weird thing however is that -- shortly after popping off the last word -- RXFLVL then gets set again and it's apparently another "OUT transfer completed" pattern. The only difference between these two "OUT transfer completed" statuses is in bit 27 (with the latter status have the bit set), but this is where STSPHST would be... but RM claims that this bit is not supported, so I should be ignoring this bit... oh what a dilemma!
But suppose we ignore table 318 for a moment and read the description of STSPHST: "Indicates the start of the status phase for a control write transfer. This bit is set along with the OUT transfer completed PKTSTS pattern." This would then explain my observation of receiving two "OUT transfer completed" statuses; one is for the completion of an OUT transfer of the data stage in the control write, while the second is to indicate the start of the status stage to finalize this control write.
Of course this just begs the question: why is the USB core designed like this?
My theory is that it's so the application can know when to enable the IN endpoint to send the status packet to the host. Despite there being the ITTXFEMSK bit ("IN token received when Tx FIFO empty mask"), this interrupt does not trigger unless the IN endpoint is already enabled (if I recall my observations correctly). In other words, there isn't really a way to know when the host has sent the IN token in order to, let's say, terminate the control write transfer early. The second "OUT transfer completed" status combined with the STSPHST bit, however, gives a way for the application to know when the host has sent the IN token to begin the status stage of the control write transfer.
This to me all sounds plausible, but the issue then is the documentation, because after all, the STSPHST bit is supposedly not even supported on the STM32L476!
Any clarifications on this would be greatly appreciated.
