USB HS DMA to external SRAM

[Piers Hawksley]

Posted on June 07, 2018 at 17:51

I'm using an STM32F723 with a customised USB driver to capture Isochronous data.

I can capture the data in 4KiB chunks. The data is DMA'd into internal SRAM then modified and copied to internal SRAM then DMA'd to an SD card. This works but I want to use larger buffers to improve SD write speeds.

I have 1MB of external SRAM that I have read / write access to. I have tested this access and used it to write dummy data to an SD card at a much higher data rate.

I am trying to DMA from the USB HS to external SRAM so I can use larger buffers - Are changes to DMA configuration needed in order to DMA to external SRAM or is there a limitation in where the USB DMA engine can DMA data to?

I've tried in 4KiB and 32Kib chunks but appear to be loosing data with the FMC write fifo disabled. With it enabled I do not get data DMA'd to external SRAM at all.

Many Thanks,

Piers

#stm32-usb-dma #dma #stm32f7-usb #stm32-f7

[waclawek.jan]

Posted on June 08, 2018 at 09:25

appear to be loosing data

Is there any pattern? Can't this be a caching problem? Is the FMC area cached?

The data is DMA'd into internal SRAM then modified and copied to internal SRAM

IMHO, if you are reading all data into mcu anyway, there's no point in using DMA to transfer from OTG's buffer into SRAM at all, except if the latencies are too big so that the input data would overflow the OTG buffer, but then I'd perhaps rather work to reduce those latencies. YMMV.

JW

[EDIT] What's the OTG's DMA burst size? Is there any change if it's reduced?

[Tesla DeLorean]

Posted on June 08, 2018 at 18:01

>>I can capture the data in 4KiB chunks. The data is DMA'd into internal SRAM then modified and copied to internal SRAM then DMA'd to an SD card. This works but I want to use larger buffers to improve SD write speeds.

I'd probably try to use as much of the DTCMRAM as possible, and hike the SDMMC clock, and see if I could get the SD card writes in the 16KB or 32KB range, beyond that the return is diminishing, and on external buses you're going to be contending for bandwidth. With the right clocking/cards a write of 5-7MBps should be possible.

[Piers Hawksley]

Posted on June 08, 2018 at 17:35

I cannot see any pattern to the data loss - it is h.264 video so it is easy to see that something is missing (blocky image etc.) but not so easy to see what

Data cache is turned off as the USB host sent zero's onto the wire for the first 20-30 bytes with the data cache enabled which the device was not too happy about - I plan to revisit this later

I'm not sure if the FMC area is cached separately - I have not spotted anything in the documentation on this (but have not looked extensively)

I think decoupling the input data (ring of buffers the DMA into) from the processing (currently just finding I and P frames) is necessary. I will try with the USB OTG DMA disabled and compare speeds

I have not been able to find where the OTG DMA burst size is set. I can freely change the buffer sizes (and how many bytes they are aligned to)

Data rate is about 2Mb/s (0.25MB/s) at present.

[Piers Hawksley]

The answer turned out to be quite simple - I had a bug in the code I was using to provide aligned buffers for the DMA engines. The code was effectively assuming that the start of the (big) buffer was aligned and providing addresses into the buffer (for each packet) correctly aligned with the start of the buffer.

Now the (effective) start of the buffer is aligned (it was in internal SRAM, but not in external SRAM) the code works as expected.

[waclawek.jan]

Thanks for coming back with the solution - and also with comments in other USB-related threads you contributed.

JW