STM32H7B3 DMA handled SPI communication. Limitation to number of request per synch event?

[HansPLJ]

I have set up a project with the STM32H7B3 where I want the LPTIM1 to generate a synchronization signal that triggers a DMA driven SPI trancieve of 6*11 bits. The SPI is set up with wordsize 11. The DMA for both rx and tx is set up in circular mode with half-word data alignment. DMA number of request is set to 6.  

In the process of getting it to work I started with only one request and it works. Increasing to 6 leads the DMA or the SPI to go into overrun. When reducing number of request to 4 it is working. 

Is there a limit to the number of request the DMA streams can handle?

The AHB1 is running at 200 MHz and the SPI clock frequncy is 20MHz. I have tried lowering the SPI clock with the same result. 

[TDK · Accepted solution]

You send 6 words to SPI when the timer is triggered? The SPI TXFIFO is only so large, can't put more in there than it can hold. Either 4 or 8 words long (with word size 11 bits) depending on the instance.

[HansPLJ]

Yes. You are right, my SPI peripheral has only 8x8 bit fifo (4 half-words). However, when I try to use the HAL_SPI_Transmit_DMA instead of HAL_SPI_TransmitReceive_DMA, it works. I am able to send 6*11 bit words at the LPTIM1 sync event. Is there a difference for the RX-fifo, compared to the TX?  

[TDK]

The excerpt I posted in the last post says the size of the RXFIFO and TXFIFO is the same.

Might need to do some debugging. "works" and "doesn't work" only gets you so far. When it "doesn't work", pause the application and examine the state of the dma handles and relevant register addresses.