/* Receive status */
ErrorStatus LL_OSPI_ReceiveRegIndirect ( OCTOSPI_TypeDef *OSPIx, OSPI_RegularCmdTypeDef *RegularCmdStruct, uint8_t *Data)
{
ErrorStatus Status = SUCCESS;
uint32_t i=0;
uint32_t Temp;
/* Wait till busy flag is reset */
while (__OSPI_GET_FLAG( OSPIx, LL_OSPI_FLAG_BUSY) == SET);
/* Put the functional mode on Indirect Read */
MODIFY_REG( OSPIx->CR, OCTOSPI_CR_FMODE_Msk, LL_OSPI_FMODE_INDIRECT_READ);
/* Modify the number of bytes to be exchanged */
MODIFY_REG( (OSPIx->DLR), OCTOSPI_DLR_DL_Msk, (RegularCmdStruct->NbData - 1U));
/* Config Transaction */
Status += OSPI_ConfigTransaction ( OSPIx, RegularCmdStruct);
/* Send instruction */
OSPIx->IR = RegularCmdStruct->Instruction;
/* Wait till fifo threshold is set to read data */
while (__OSPI_GET_FLAG( OSPIx, LL_OSPI_FLAG_FT) == RESET);
do
{
/* Receive register data */
Temp = OSPIx->DR;
Data [i] = (uint8_t) Temp;
i = i+1;
} while (i < RegularCmdStruct->NbData);
/* so wait until TC flag is set to go back in idle state */
while (__OSPI_GET_FLAG( OSPIx, LL_OSPI_FLAG_TC) == RESET);
/* Clear transfer complete flag */
__OSPI_CLEAR_FLAG( OSPIx, LL_OSPI_FLAG_TC);
/* Return function status */
return Status;
}
The code runs to the end but returns the wrong data. I debugged it with JTAG probe and found
that while the FIFO flag sets correctly and before putting the DR register in Temp variable
SR->FLEVEL is at 5, after the first read it goes to zero! Isn't it the case that if I have
5 bytes in FIFO I should access the OSPI->DR, 5 times? I put the data temporarily in Temp
variable to make sure that I don't read 4 bytes at a time.
