STM32F7 ethernet PTP PPS to timer 2

[LCE]

Hello,

I just got lwIP with PTPd on 2 Nucleo-144 with STM32F767ZI working.

Thanks to all the open source people out there!

PPS output is also working, I use these signals to check sync quality on a scope.

PPS from ETH goes to TIM2 via ITR1 input to TRGO to GPIOB pin 5.

So far so good...

Now I would like to use that PPS signal internally, but I don't get it to work within timer 2.

Neither as a counter reset signal, nor as a clock source for timer 2.

First I started using the HAL stuff, then I set all the registers (CR1, SMCR, DIER and more) "manually" - nothing!

Is there anything they forgot to mention in the datasheet / ref manual?

Right now it seems to me that this PPS signal is only routed to the TRGO output and can NOT be used otherwise by timer 2.

Anybody an ideas?

Thanks in advance!

[Piranha · Accepted solution]

Hello!

I tested and figured this out. There are two separate timing signals from the PTP module:

• PTP trigger. The target time is set in a ETH_PTPTTHR and ETH_PTPTTLR registers. This one is connected to TIM2 ITR1.
• PPS output. The frequency is set in a ETH_PTPPPSCR_PPSFREQ bit field. This one is connected to ETH_PPS_OUT.

The whole misunderstanding is because of a documentation error.

RM0410 Rev 4 page 1806, paragraph "PTP trigger internal connection with TIM2" is true:

This PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The connection is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR). Figure 565 shows the connection.

RM0410 Rev 4 page 1807, paragraph "PTP pulse-per-second output signal" is false:

The PPS output is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR).

An interesting fact is that F2 series (RM0033 Rev 9 page 880) and F4 series (RM0090 Rev 19 page 1163) have a correct PPS output description:

The PPS output is enabled through a GPIO alternate function. (GPIO_AFR register).

Obviously the F7 reference manual is based on F4/F2 manuals. I just wonder why someone "corrected" that description to the wrong one.

@Imen DAHMEN​

[Piranha]

Noticed some other errors in RM0410 Rev 4.

Page 1866, ETH_PTPTTHR description:

The Target time high register, along with Target time low register, is used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time exceeds the value programmed in these registers.

TSARU bit has nothing to do with this. The description means TSITE bit.

Also there are two places, where the TSARU bit is named wrongly as TTSARU - pages 1860 and 1884. The Ctrl+F will show exactly where...

[LCE]

@Piranha​ Thank you so much for testing and figuring this out!

And here comes the bitter part for me:

I completely misunderstood the meaning of the PTP trigger - I was so sure that this signal was the same as - or at least could be - the PPS output.

Shame on me... :(

Shows me again what I like to tell other people: RTFM! And that carefully and with brain switched on.

But this explains why sometimes I could see that TIM2 counted exactly once - that must have been when the target time interrupt was triggered, which I use after successful PTP sync just to sync the LED blinking on the 2 Nucleo boards.

At least I got that right...

[Imen.D]

Hello @Piranha​ ,

Thank you for bringing this post to my attention.

I really appreciate your collaboration with @Community member​, and your answer has been very helpful.

I escalated the internal ticket (ID 118901) to involved team to correct the errors.

(PS: The internal ticket ID 118901 is an internal tracking number and is not accessible or usable by customers).

Thanks

Imen