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STM32F4 MCU ST SelfTest Error(STL_MainClockTest)

MW_JANG
Associate

We are currently using the ST32F4 MCU.
During operation, we are using self-diagnostic code provided by ST, but after 8 days of normal operation, an EXT_SOURCE_FAIL occurs in STL_MainClockTest(), causing the MCU to reset.

When EXT_SOURCE_FAIL does not occur, the PeriodValue is measured between 11,500 and 11,800. However, when the error occurs, the PeriodValue is around 23,000, approximately twice the normal value.

The function for calculating the Period Value is as follows:

 

MW_JANG_2-1731378154897.png

HSE is operating at 25MHz, and LSI is operating at 32kHz.
We are using TIM5's Ch4 for INPUT Capture, and the detailed settings for INPUT Capture are as follows:

 

MW_JANG_4-1731378259914.png

  • Questions:

    1. We are currently using tim_input_config.ICPrescaler with TIM_ICPSC_DIV4. Is it acceptable to change it to TIM_ICPSC_DIV8?
    2. What is the difference between TIM_ICPSC_DIV4 and TIM_ICPSC_DIV8?
    3. What is the meaning of the ICFilter value, and could changing it prevent errors?

 

2 REPLIES 2
Amel NASRI
ST Employee

Hi @MW_JANG ,

Your request is shared with our expert (Internal request number 196225).

We will come back to you soon after analyzing your request.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Petr Sladecek
ST Employee

Hello,

the open source example of the clock cross check measurement comes from previous obsolete version of the library. It shows a possible way of implementation measurement required by the standard (Item 3 at Table R1 of 60335-1:Annex R). The faster system clock is gated by slower source (LSI) while sequence of 8 consecutive periods of LSI (set as IPSC divider) is applied to do a single measurement. Number of the gated pulses of system clock is then compared if it fits into expected interval defined here as fixed low limit and high limit constants (see definition of macros CLK_LimitHigh and CLK_LimitLow). If you want to gate shorter interval, you need to adapt these macros, of course. Note when appli runs under XTAL, it is enough to detect harmonic and subharmonic fcy failures.

The problem is the LSI drifts with temperature significantly so you need to operate with adaptable limit range as explained at the attached presentation.

Best regards,

Petr