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[STM32CubeMX] lwIP + FreeRTOS Sample Project

emeydanli
Associate II
Posted on April 23, 2014 at 16:41

Hello Everyone,

I wonder if anyone has been able to get lwIP work properly?

My platform consists of Open407-D baseboard, STM32F4 Discovery and DP83848 Ethernet PHY. SysClk is clocked at 168 MHz.

I have been struggling with generated code by STM32CubeMX for two days. During this time, I have found several issues. 

1) In sys_mutex_lock function, mutex pointer seems incorrectly dereferenced.

2) Priority of the ethernet interrupt is incorrectly configured. It is higher than configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY. That's why firmware hangs in one of FreeRTOS assertions.

3) tcpip_thread is not created due to an incorrect parameter value. (TCPIP_THREAD_STACKSIZE equals to zero)

These are the things I could find but still I cannot get it work. Even though the DHCP option is enabled, the device cannot get an IP address. Giving a static IP address does not work too.

The worst thing is it does not even respond to pings. As an experiment, I created an UDP socket and sent data over it continuously. Green Ethernet LED blinks but of course the packets do not reach to anywhere. (checked with wireshark) 

What can be the problem? Do you have any ideas?

#freertos-lwip #stm32-discovery #cube-lwip-+-stm32f107-+-lan8720a #ethernet
40 REPLIES 40
antonius
Senior
Posted on July 23, 2015 at 23:52

Clive1, this is what I get from ARP, looks like I haven't got IP for STM32 ?

I can't find 1.12 ??? How do you reckon ?

C:\Users\antonius>ping 1.12
Pinging 1.12 with 32 bytes of data:
Reply from 1.10: Destination host unreachable.
Request timed out.
Request timed out.
Request timed out.
Ping statistics for 1.12:
Packets: Sent = 4, Received = 1, Lost = 3 (75% loss),
C:\Users\antonius>arp -av
Interface: 0.0.1 --- 0x1
Internet Address Physical Address Type
0.0.22 static
250 static
Interface: 0.0.1 --- 0xa
Internet Address Physical Address Type
0.0.138 00-26-44-a0-e1-e6 dynamic
0.0.255 ff-ff-ff-ff-ff-ff static
0.0.22 01-00-5e-00-00-16 static
0.0.252 01-00-5e-00-00-fc static
250 01-00-5e-7f-ff-fa static
255 ff-ff-ff-ff-ff-ff static
Interface: 1.10 --- 0xb
Internet Address Physical Address Type
1.1 00-00-00-00-00-00 invalid
1.12 00-00-00-00-00-00 invalid
1.255 ff-ff-ff-ff-ff-ff static
0.0.22 01-00-5e-00-00-16 static
0.0.252 01-00-5e-00-00-fc static
250 01-00-5e-7f-ff-fa static
Interface: 0.0.0.0 --- 0xffffffff
Internet Address Physical Address Type
0.0.22 01-00-5e-00-00-16 static
255 ff-ff-ff-ff-ff-ff static
Interface: 1 --- 0x14
Internet Address Physical Address Type
255 ff-ff-ff-ff-ff-ff static
0.0.22 01-00-5e-00-00-16 static
0.0.252 01-00-5e-00-00-fc static
250 01-00-5e-7f-ff-fa static
Interface: 1 --- 0x15
Internet Address Physical Address Type
255 ff-ff-ff-ff-ff-ff static
0.0.22 01-00-5e-00-00-16 static
0.0.252 01-00-5e-00-00-fc static
250 01-00-5e-7f-ff-fa static
Interface: 0.0.0.0 --- 0xffffffff
Internet Address Physical Address Type
0.0.22 01-00-5e-00-00-16 static
C:\Users\antonius>

antonius
Senior
Posted on July 26, 2015 at 01:58

Is it because of the setting of RCC ? I used from STM32CubeMx RCC seting configurator....

Posted on July 26, 2015 at 02:19

Is it because of the setting of RCC ? I used from STM32CubeMx RCC setting configurator....

No idea, I don't even know if the hardware design is viable, having no insight into the schematic or BOM.

If you think it's a software problem you could look at SPL and STM3210C-EVAL examples. For hardware the counter point would be someone elses working board/design.
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antonius
Senior
Posted on July 26, 2015 at 05:32

================

The debugging output would be a lot more effective if it specified the length of the buffer received and output the buffer as hex bytes. At an ETH 83 level this would let you see source and destination MAC addresses on the wire, and if you dug deeper the TCP/IP payload beyond them. ================ do you mean the value of this ? /* Obtain the size of the packet and put it into the ''len'' variable. */ len = heth.RxFrameInfos.length; buffer = (uint8_t *)heth.RxFrameInfos.buffer;

/**
* Should allocate a pbuf and transfer the bytes of the incoming
* packet from the interface into the pbuf.
*
* @param netif the lwip network interface structure for this ethernetif
* @return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf * low_level_input(struct netif *netif)
{
struct pbuf *p = NULL;
struct pbuf *q;
uint16_t len = 0;
uint8_t *buffer;
__IO ETH_DMADescTypeDef *dmarxdesc;
uint32_t bufferoffset = 0;
uint32_t payloadoffset = 0;
uint32_t byteslefttocopy = 0;
uint32_t i=0;
/* get received frame */
if (HAL_ETH_GetReceivedFrame(&heth) != HAL_OK)
return NULL;
/* Obtain the size of the packet and put it into the ''len'' variable. */
len = heth.RxFrameInfos.length;
buffer = (uint8_t *)heth.RxFrameInfos.buffer;
if (len > 0)
{
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
}
if (p != NULL)
{
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
bufferoffset = 0;
for(q = p; q != NULL; q = q->next)
{
byteslefttocopy = q->len;
payloadoffset = 0;
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
{
/* Copy data to pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
bufferoffset = 0;
}
/* Copy remaining data in pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
}
/* Release descriptors to DMA */
/* Point to first descriptor */
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (i=0; i< 
heth.RxFrameInfos.SegCount
; i++)
{ 
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
}
/* Clear Segment_Count */
heth.RxFrameInfos.SegCount =0;
} 
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) 
{
/* Clear RBUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_RBUS;
/* Resume DMA reception */
heth.Instance->DMARPDR = 0;
}
return p;
}

Here's the buffer value I got : 0690X0000060332QAA.jpg
antonius
Senior
Posted on July 29, 2015 at 11:28

clive,

My board is using 8MHz external crystal, may be it's the cause ?

I saw in on design , I must use 25MHz with this method...

0690X00000602tmQAA.jpg

HCLK value ? Must be 25MHz ? thanks

Posted on July 29, 2015 at 14:28

My board is using 8MHz external crystal, may be it's the cause ? I saw in on design , I must use 25MHz with this method...

I don't believe it's a requirement, it does permit designs with a single crystal. What does have to happen is that you change default settings for the PLL and HSE_VALUE, so they are consistent/coherent with the clock source you are providing.

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antonius
Senior
Posted on July 29, 2015 at 15:02

Is my clock configuration acceptable ?

I make it with STM32CubeMx

0690X000006033CQAQ.jpg

antonius
Senior
Posted on July 30, 2015 at 14:25

guys,

can I see my connection status from this function ? Which function / register is describing MAC address ?? Thanks

/**
* @brief Reads a PHY register
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module 
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
* This parameter can be one of the following values: 
* PHY_BCR: Transceiver Basic Control Register, 
* PHY_BSR: Transceiver Basic Status Register. 
* More PHY register could be read depending on the used PHY
* @param RegValue: PHY register value 
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)

Posted on July 30, 2015 at 15:11

The DP83848 manual should contain the register/bit definitions.

Not sure why you're clocking the CPU at 50 MHz, I'd think the PLL would permit 72 MHz operation. Assuming your PHY has it's own crystal, lacking a schematic.
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antonius
Senior
Posted on July 30, 2015 at 16:26

The Schematic, I changed the crystal of STM32 to 25MHz...and see what happens...

0690X000006033RQAQ.jpg

STM32 schematic, I changed to STM32F107VCT6 and 25MHz crystal

0690X00000602zuQAA.jpg