2021-12-01 02:38 PM
I'm following the bootloader ACK procedure outlined in AN4286, page 6.
The issue I'm having is that the bootloader never responds with 0x79 (ACK) or 0x1F (NACK) after the initial synchronization (Sent 0x5A, Received 0xA5).
Are there any issues with my understanding of the procedure? I'm assuming the dummy byte first sent by the bootloader is supposed to be used throughout the procedure?
I'm using STM32H750B-DK with erased flash memory, and proper PI0, PI1, PI2, PI3 pins for SPI2 as outlined in AN2606, page 263.
SCK is pulled down to GND with a 10k resistor, NSS is pulled down at the start of every transaction (tying it to GND as suggested in the docs seems to work worse).
Seems like a similar issue to post, but not the same Cannot get into the factory ST bootloader from AN2606 for programming over.
Solved! Go to Solution.
2021-12-08 11:13 AM
Able to get to ACK by sending 0x00 instead of the initial dummy byte, but it takes 40 attempts.
2021-12-01 03:21 PM
What's the time scale here? Are you waiting 8+us between the first and second byte as required per AN2606?
2021-12-01 03:24 PM
Yes, the interval between the transfers (on the right side of the image) is 1ms.
2021-12-01 03:29 PM
It would be nice to see the full scope trace from reset. You have stuff happening before the sync byte which makes me think it may already be in the bootloader. The sync frame is only done once to enter the SPI bootloader.
2021-12-01 03:35 PM
Here's the different but equally disappointing results when using SPI1 (PA4, 5, 6, 7).
2021-12-01 04:58 PM
Here's the trace from reset.
2021-12-01 05:30 PM
And the same result for SPI3 (PC12, 11, 10, PA15).
2021-12-01 06:04 PM
Seems like my understanding is correct as it matches the behavior in this SPI bootloader host implementation.
2021-12-02 02:49 PM
Getting essentially the same result when using an another STM32H7 as a bootloader host. Just running the example from the implementation in the previous post.
2021-12-03 11:19 AM