2021-05-20 02:44 AM
I have a question about the usage of the Cache in a Bootloader for the STM32H730
I am using:
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
__enable_irq();
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_DMA_Init();
MX_CRC_Init();
MX_OCTOSPI1_Init();
/* USER CODE BEGIN 2 */
...
*init QSPI*
*set QSPI to memory mapped mode*
...
/* Disable all interrupts */
NVIC->ICER[0] = NVIC->ICER[1] = NVIC->ICER[2] = NVIC->ICER[3] = NVIC->ICER[4] = NVIC->ICER[5] = 0xFFFFFFFF;
SCB_DisableICache();
SCB_DisableDCache(); /************* DOES NOT WORK ***************/
SysTick->CTRL = 0;
*jump to application*
}
My Problem:
My Question:
Thank you for any help!
Solved! Go to Solution.
2021-05-21 05:18 AM
Problem is described here already: https://github.com/ARM-software/CMSIS_5/issues/620
Solution:
2021-05-21 04:09 AM
Update:
I noticed that the SCB_DisableDCache() run properly if I do it before HAL_InitTick().
Could it be that the settings in HAL_InitTick come from an older project that and do not match the current STMH7?
2021-05-21 04:49 AM
Hi @Hueli.1 ,
Are you using DTCM/ITCM ?
Ons.
2021-05-21 05:16 AM
I don't think so. While the ITCM and DTCM sections are defined like the following there is no .itcm part (does this mean it's not used?):
DTCMRAM (xrw) : ORIGIN = 0x20000000 + 0x30, LENGTH = 128K - 0x30
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
However I think I have found the solution to the problem. See response to my original post
2021-05-21 05:18 AM
Problem is described here already: https://github.com/ARM-software/CMSIS_5/issues/620
Solution:
2021-05-22 09:14 AM
Bootloader must be as simple and robust as possible and it's performance is not critical. Therefore to avoid both software and hardware issues for bootloader it is highly recommended to not use cache memories at all.
2022-07-19 12:21 AM
This commit to the CMSIS repository fixes it properly.
2022-07-19 12:47 AM
Expect it to be updated in ST's code base in the next 5 years. 😉 For F7 series they are still shipping a version from 2018 with broken cache management functions, which were fixed in the same 2018 few months later.
And read my other comment...
2024-08-11 11:47 PM
Also relevant (same problem): https://community.st.com/t5/stm32-mcus-products/boot-application-issue-with-scb-disabledcache/td-p/298477