OpenOCD does not bypass data cache

[mkrk]

I'm using STM32H7S78-DK and STM32CubeIDE v1.17.0. I was try to get Segger RTT working so I switched from ST-Link GDB server to OpenOCD because it has in-built RTT telnet server, but couldn't because OpenOCD didn't find RTT area.

I reduced the problem down to this simple example and realized it's related with data cache:

volatile uint32_t test = 1;

int main(void)
{
  test = 2;
  SCB_EnableDCache();
  test = 3;
  HAL_Init();

When debugging it with ST-link "test" will be 3 at line 8. When running with OpenOCD, test will remain 2. When not enabling cache, "test" will be 3.

I used default CubeIDE OpenOCD configuration and checked all the flags. I haven't had a problem with OpenOCD and STM32H5/H7 series with enabled cache before.

I found similar issue report from SO: https://electronics.stackexchange.com/questions/552477/debugging-cortex-m7-with-data-cache

There's one answer saying to monitor using_hla. I didn't get any response for that command in GDB console.

[Pavel A.]

So all these complications are because wanting to use RTT. Why do you want it? Can the ITM (SWO) output replace it? Just call printf?

[mkrk]

Good point, I will soon try other methods also, but it often tends to happen that, if you leave something unfixed, someone else or yourself in the future, will hit the same problem and waste time again. And the issue is not with just RTT, whole OpenOCD debugger is useless if it can't show the cached values what the CPU sees and operates on. I may have reported it under OpenOCD project, but I tried latest xPack OpenOCD and that does not have this chip full support. ST delivered OpenOCD comes with larger device files which indicates that they have obviously added this chip support.

[Pavel A.]

ST is involved in development of  OpenOCD. You can send a bug report.