Unable to configure 100MHz Clock with CMSIS

[Yash Jasnani]

Dear Experts,

I need your help to configure the clock using CMSIS. I am using Nucleo 64 board of STM32F411RE. 

Steps I have followed:-

1. Enable PWR CLK.

2. SET VOS value to 3.

3. Enable Prefetch, Instruction cache, Data cache.

4. Set Flash Latency 3WS.

5. SET HSE Bypass.

6. Enable HSE CLK.

7. Wait for HSE RDY Flag.

8. Set PLL Prescaler values.

9. Enable PLL.

10. Wait for PLL RDY Flag.

11. Select System CLK as PLL.

12. Check status of System CLK Source. (SWS bits)

13. Set APB1 Prescaler to div 2.

14. Disable HSI CLK.

/**
 ******************************************************************************
 * @file           : main.c
 * @author         : Auto-generated by STM32CubeIDE
 * @brief          : Main program body
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2024 STMicroelectronics.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */

#include <stdint.h>
#include <stdio.h>
#include "stm32f4xx.h"
#include "stm32f411xe.h"

int _write(int file, char *ptr, int len)
{
  int i=0;
  for(i=0 ; i<len ; i++)
    ITM_SendChar((*ptr++));

  return len;
}

//#if !defined(__SOFT_FP__) && defined(__ARM_FP)
//  #warning "FPU is not initialized, but the project is compiling for an FPU. Please initialize the FPU before use."
//#endif
uint32_t SystemCoreClock = 100000000; //100MHz

int main(void) {
	/* Loop forever */

	//Enable GPIOA CLK
	SET_BIT(RCC->AHB1ENR,RCC_AHB1ENR_GPIOAEN);
	//Enable GPIOb CLK
	SET_BIT(RCC->AHB1ENR,RCC_AHB1ENR_GPIOBEN);

	//Set High Speed for PA8
	MODIFY_REG(GPIOA->OSPEEDR,
			GPIO_OSPEEDR_OSPEED8,
			_VAL2FLD(GPIO_OSPEEDR_OSPEED8,3));

	//Set AF mode for PA8
	MODIFY_REG(GPIOA->MODER,
			GPIO_MODER_MODER8,
			_VAL2FLD(GPIO_MODER_MODER8,2));

	while(1){
		printf("Hello\r\n");
		for(int i = 0; i<1000000;i++);
	}
}

void SystemInit(void) {

	//Enable PWR CLK
	SET_BIT(RCC->APB1ENR,RCC_APB1ENR_PWREN);

	//Set Regulator voltage scale mode for 100MHz
	MODIFY_REG(PWR->CR,
			PWR_CR_VOS,
			_VAL2FLD(PWR_CR_VOS,3));

	//Enable prefetch, Instruction cache, data cache
	SET_BIT(FLASH->ACR,
			FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN);

	//Set Flash Latency 3WS
	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY,
			_VAL2FLD(FLASH_ACR_LATENCY,FLASH_ACR_LATENCY_3WS));

	//Set MCO1 Prescaler to div 2
	MODIFY_REG(RCC->CFGR,
			RCC_CFGR_MCO1PRE,
			_VAL2FLD(RCC_CFGR_MCO1PRE,4));

	//Select MCO1 source as PLL
	SET_BIT(RCC->CFGR, RCC_CFGR_MCO1);

	//SET HSE Bypass
	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
	//Enable HSE CLK
	SET_BIT(RCC->CR, RCC_CR_HSEON);
	//Wait for HSE to get stable
	while (!READ_BIT(RCC->CR, RCC_CR_HSERDY))
		;

	//Set PLL Prescaler values
	MODIFY_REG(RCC->PLLCFGR,
			RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLSRC,
			_VAL2FLD(RCC_PLLCFGR_PLLM,4) | _VAL2FLD(RCC_PLLCFGR_PLLN,100) | _VAL2FLD(RCC_PLLCFGR_PLLP,2) | RCC_PLLCFGR_PLLSRC_HSE);
	//Enable PLL
	SET_BIT(RCC->CR, RCC_CR_PLLON);
	//Wait for PLL to get stable
	while (!READ_BIT(RCC->CR, RCC_CR_PLLRDY))
		;

	//Select System Clk as PLL
	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, _VAL2FLD(RCC_CFGR_SW,RCC_CFGR_SW_PLL));


	//check status of system clk source
	while (READ_BIT(RCC->CFGR,RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
		;

	//Set APB1 Prescaler to div 2
	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_CFGR_PPRE1_DIV2);

	//Disable HSI CLK
	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
}

[waclawek.jan]

What are the symptoms and how are they different from the expectations?

Have you single-stepped the code and observed the RCC registers' content?

JW