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NUCLEO-U5A5ZJ-Q and nRF7002 interface using vanillas Zephyr

ElectrifyServices
Associate II

Hello STM team,

 

We are working to interface the  NUCLEO-U5A5ZJ-Q and nRF7002-DK using QSPI. We are using vanillas zephyr. We are able to built the code for SPI. But can not be able to built for QSPI. It will be very helpful if you provide a proper support to interface this.

17 REPLIES 17
Andrew Neil
Super User

Welcome to the forum.

Please give some more details of your setup - see:

How to write your question to maximize your chances to find a solution

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.
ElectrifyServices
Associate II

IDE: vanilla zephyr

STM32: NucleoU5A5ZJ-Q

nRF-wifi: nRF7002-DK kit

Interface protocol: QSPI

Code: Shell test code (From list of example code in IDE)

 

I am able to built the shell code for STM32 successfully. That is working on SPI protocol.

I want to use QSPI protocol. For that I have added the overlay file to configure the QSPI pins of the NucleoU5A5ZJ (Overlay file is attached already). In overlay file the nRF7002 accepts the SPI, QSPI or Coaxe instance. And NucleoU5A5ZJ is having OctoSPI.

/*
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */
/ {
	chosen {
		zephyr,wifi = &wlan0;
	};
};

&octospi1 {
	pinctrl-0 = <&octospim_p1_clk_pa3 &octospim_p1_ncs_pa2 &octospim_p1_dqs_pa1
				 &octospim_p1_io0_pb1 &octospim_p1_io1_pb0 
				 &octospim_p1_io2_pa7 &octospim_p1_io3_pa6  
				 &octospim_p1_io4_pc1 &octospim_p1_io5_pc2
				 &octospim_p1_io6_pc3 &octospim_p1_io7_pc0>;

	pinctrl-names = "default";

	dmas = <&gpdma1 0 7 0x10440>,
		   <&gpdma1 1 6 0x10480>;
	dma-names = "tx","rx";

	nrf70: &octospi1 {
		compatible = "nordic,nrf7002-spi";
		status = "okay";
		reg = <0>;
 
		/* Control GPIOs - using available pins that don't conflict */
		iovdd-ctrl-gpios = <&gpiob 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* D0 */
		bucken-gpios = <&gpiob 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;     /* D1 */
		host-irq-gpios = <&gpiog 12 GPIO_ACTIVE_HIGH>;                     /* D7 */
		/* List of interfaces */
		wlan0: wlan0 {
			compatible = "nordic,wlan";
		};
		/* Wi-Fi TX power limits */
		wifi-max-tx-pwr-2g-dsss = <21>;
		wifi-max-tx-pwr-2g-mcs0 = <16>;
		wifi-max-tx-pwr-2g-mcs7 = <16>;
		wifi-max-tx-pwr-5g-low-mcs0 = <13>;
		wifi-max-tx-pwr-5g-low-mcs7 = <13>;
		wifi-max-tx-pwr-5g-mid-mcs0 = <13>;
		wifi-max-tx-pwr-5g-mid-mcs7 = <13>;
		wifi-max-tx-pwr-5g-high-mcs0 = <12>;
		wifi-max-tx-pwr-5g-high-mcs7 = <12>;
	};

	status = "okay";
};

// &spi1 {
// 	status = "okay";
// 	pinctrl-0 = <&spi1_sck_pa1 &spi1_miso_pa11 &spi1_mosi_pa12>;
// 	pinctrl-names = "default";
// 	cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
// 	/* High speed SPI configuration for STM32H7 */
// 	clock-frequency = <DT_FREQ_M(50)>; /* 50MHz SPI clock */
 
// 	nrf70: nrf7002-spi@0 {
// 		compatible = "nordic,nrf7002-spi";
// 		status = "okay";
// 		reg = <0>;
// 		spi-max-frequency = <DT_FREQ_M(8)>; /* Increased from 8MHz to 16MHz */
 
// 		/* Control GPIOs - using available pins that don't conflict */
// 		iovdd-ctrl-gpios = <&gpiob 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* D0 */
// 		bucken-gpios = <&gpiob 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;     /* D1 */
// 		host-irq-gpios = <&gpiog 12 GPIO_ACTIVE_HIGH>;                     /* D7 */
// 		/* List of interfaces */
// 		wlan0: wlan0 {
// 			compatible = "nordic,wlan";
// 		};
// 		/* Wi-Fi TX power limits */
// 		wifi-max-tx-pwr-2g-dsss = <21>;
// 		wifi-max-tx-pwr-2g-mcs0 = <16>;
// 		wifi-max-tx-pwr-2g-mcs7 = <16>;
// 		wifi-max-tx-pwr-5g-low-mcs0 = <13>;
// 		wifi-max-tx-pwr-5g-low-mcs7 = <13>;
// 		wifi-max-tx-pwr-5g-mid-mcs0 = <13>;
// 		wifi-max-tx-pwr-5g-mid-mcs7 = <13>;
// 		wifi-max-tx-pwr-5g-high-mcs0 = <12>;
// 		wifi-max-tx-pwr-5g-high-mcs7 = <12>;
// 	};
// };

Problem statement: Need to know how can we connect the OctoSPI with the nRF7002 in the overlay file. We tried to use OctoSPI instance with nRF7002, but it throughs error when built.

nRF accept SPI, QSPI or Coaxe instance only.

While NucleoU5A5ZJ supports SPI and OctoSPI.

Please show the schematic of how you have the nRF7002 connected to the Nucleo.

 

Is the nRF7002 on an eval board, or similar?

EDIT: It's an nRF7002-DK - see follow-up questions below.

 


@ElectrifyServices wrote:

I am able to built the shell code for STM32 successfully. That is working on SPI protocol.


So you have the nRF7002 working OK in SPI mode?

 


@ElectrifyServices wrote:

We tried to use OctoSPI instance with nRF7002, but it throughs error when built.


Please show the error(s) that you get.

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

@Andrew Neil wrote:

Is the nRF7002 on an eval board, or similar?


Sorry, you did say it's an nRF7002-DK.

So this: https://www.nordicsemi.com/Products/Development-hardware/nRF7002-DK

 

That kit includes an nRF5340 SoC as host processor for the nRF7002 - so are you sure you've fully disconnected that to allow your STM32 to be the host?

Have you confirmed your hardware setup with Nordic?

https://devzone.nordicsemi.com/

 

PS:

Have you got OctoSPI working with the nRF5340 ?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.
Pavel A.
Super User

Documentation brief for the nRF7002-DK says that the DK has its own host MCU.

There's no indication that the nRF7002 chip of the DK can be connected to external host.

 

 

Hello Andrew,

Thanks for putting your efforts to solve this issue.

I have not run and test the SPI code on the hardware setup yet. As that is not my final goal. I have just built the SPI code in vanilla zephyr IDE. If this testing is required then I can do it. No issues.

As my final goal is to run nRF7002 using QSPI (quad SPI) using STM32 NucleoU5A5ZJ-Q as host MCU. So after building the SPI code successfully, I jump to work on implementing the QSPI. For QSPI, I add the overlay file to assign the QSPI hardware instance with nRF7002, in that I am getting the error at time of built.

 

Problem statement: How to port the SPI code to work on QSPI.

For your reference: I am working on the shell example code of the vanilla zephyr IDE. And the built is set for  STM32 NucleoU5A5ZJ-Q.

Hello Pavel,

Yes, the nRF7002-DK has the nRF5340 as the on board host MCU.

I have not run the code on the hardware setup yet. I need to check the nRF7002-DK documents for that.

I have ordered the nRF7002-EK already. Once I receive that board I can test on it. This is just to get start with existing hardware available with me.

I would certainly start by getting it working with nRF5340  using QSPI - then you will have a reference point for your STM32 port.

As @Pavel A. also said, you need to confirm with Nordic that the nRF7002 can be completely isolated from the nRF5340 on that DK - and how to do that.

 

Have you checked CubeMX and/or the STM32CubeU5 firmware pack for QSPI examples ?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

I have tested the nRF7002 and nRF5340 interface using QSPI protocol. And that is working fine.

I will check the nRF7002-DK, test it and will let you know.