Is there a complete/correct STM32H73x.svd file anywhere?

[CGran.3]

I have the STM32H73x.svd from then STMCubeH7 pack version 1.9.0 but it is far from compete/correct.

Some examples

AHB3 clock enable /reset registers do not have any of the OCTOSPI items in there, but has a QSPI entry.

Similar some timer enables/reset are in the same case (23 and 24 specifically)

the Flash ACR register field for Latency is the incorrect length (3 when it should be 4)

[CGran.3]

@Mike_ST​ 

I pulled down a few different sources and looked in that location as well. All instances seem to be the same and missing data. I was hoping not to have to edit them myself to get them up to date.

[Mike_ST]

Yes. it is same ticket.

[CGran.3]

@Mike_ST​ 

Thanks,

It appears the Delay Block Bypass (DLYBYP) is also missing for the OCTOSPI DCR1 Register and the DCR4 register is of the incorrect length for the refresh field. (16 vs 32 bits)

[Mike_ST]

Yes, thank you. I added this in the ticket.

I guess the team in charge of this ticket will do a rework/review of the entire file.

[Tesla DeLorean]

Having to manually edit and fix this stuff does seem highly unsatisfactory. Someone needs to be responsible for doing some proper validation and cross checking with the gate level implementation​. And also fix/validate the RM issues.

[JCH]

@Mike_ST​ : Could you please also update OTG_HS register description? At least the description of OTG_HS_GOTGCTL is not complete, others probably as well. I'm using an STM32H743. The SVD ist STM32H743.svd which comes from the Keil STM32H7xx_DFP version 3-0-0. It is the same file that can also be downloaded from the ST homepage (CAD section) directly (see above).

[Mike_ST]

Ok, I've added that in the ticket.

[Mike_ST]

Update: SVD have been updated since.

Ticket is closed.

[Piranha]

It took "just" a little less than two years. Great timing! 😉