2018-08-25 04:58 AM
Hi,
I am migrating some USB code which was initially developed on STM32F0.
There are 6 end points in use (including control):
EP address:
0x0
0x80
0x87 -
0x81
0x01
0x82
So my code to config PMA in USB_LL_Init:
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x87, PCD_SNG_BUF, 0x98);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81, PCD_SNG_BUF, 0xD8);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01, PCD_SNG_BUF, 0x13C);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82, PCD_SNG_BUF, 0x1A0);
and this works fine on STM32F0.
Now I am migrating this same code to STM32F4 and here is a bit different. Using HAL_PCDEx_SetRxFiFo and HAL_PCDEx_SetTxFifo. As below:
HAL_PCDEx_SetRxFiFo(&hpcd_USB_FS, 0x40);
HAL_PCDEx_SetTxFiFo(&hpcd_USB_FS, 0, 0x40); // EP0
So my understanding is that my old code translates into something like this:
HAL_PCDEx_SetRxFiFo(&hpcd_USB_FS, 0x40); // 0x0
HAL_PCDEx_SetTxFiFo(&hpcd_USB_FS, 0, 0x40); // 0x80
HAL_PCDEx_SetTxFiFo(&hpcd_USB_FS, 7, 0x40); // 0x87
HAL_PCDEx_SetTxFiFo(&hpcd_USB_FS, 1, 0x40); // 0x81
HAL_PCDEx_SetTxFiFo(&hpcd_USB_FS, 2, 0x40); // 0x82
Is this correct or am I missing something?
2018-08-25 07:04 AM
I don't use Cube/HAL, but these functions might expect size in words, and might be expected to be called in a rigorous order, i.e. Rx first, then Tx in their natural order.
You also need the common Rx buffer be big enough to accomodate the biggest Out packet (plus some overhead).
JW
2018-08-31 07:04 AM
I made general mistake. Number coresponds to pipe address. F4 ha 5In/OUT EP. RX fifo is common and TX can be assigned to each EP.
So digging into CMSIS drivers they predefine FIFO's with constant values.
Dividing 1.25k by two. One half is RX fifo and other half divides to another 5 for each TX EP.
So a call shoud be
HAL_PCDEx_SetTxFiFo(&hpcd_USB_FS, x, 0x40); where x goes from 0 to 5.
and coresponds to addresses 0x80...0x85
What I did in my project is switch of EP 0x87 to 0x83 and it works fine.
2018-12-11 10:46 PM
Hello Nix
I'm in the same situation porting code but from STM32F4 to STM32F7.
Can you please clearify how it works ??
I have
HAL_PCDEx_PMAConfig(pdev->pData , RNDIS_CONTROL_OUT_EP , PCD_SNG_BUF, RNDIS_CONTROL_OUT_PMAADDRESS);
HAL_PCDEx_PMAConfig(pdev->pData , RNDIS_CONTROL_IN_EP , PCD_SNG_BUF, RNDIS_CONTROL_IN_PMAADDRESS);
HAL_PCDEx_PMAConfig(pdev->pData , RNDIS_NOTIFICATION_IN_EP , PCD_SNG_BUF, RNDIS_NOTIFICATION_IN_PMAADDRESS);
HAL_PCDEx_PMAConfig(pdev->pData , RNDIS_DATA_OUT_EP , PCD_SNG_BUF, RNDIS_DATA_OUT_PMAADDRESS);
HAL_PCDEx_PMAConfig(pdev->pData , RNDIS_DATA_IN_EP , PCD_SNG_BUF, RNDIS_DATA_IN_PMAADDRESS);
where
define RNDIS_CONTROL_OUT_EP 0x00
#define RNDIS_CONTROL_IN_EP 0x80
#define RNDIS_NOTIFICATION_IN_EP 0x81
#define RNDIS_DATA_IN_EP 0x82
#define RNDIS_DATA_OUT_EP 0x03
and
#define RNDIS_CONTROL_OUT_PMAADDRESS 0x08 * 4 //8 bytes per EP
#define RNDIS_CONTROL_IN_PMAADDRESS RNDIS_CONTROL_OUT_PMAADDRESS + USB_MAX_EP0_SIZE
#define RNDIS_NOTIFICATION_IN_PMAADDRESS RNDIS_CONTROL_IN_PMAADDRESS + USB_MAX_EP0_SIZE
#define RNDIS_DATA_IN_PMAADDRESS RNDIS_NOTIFICATION_IN_PMAADDRESS + RNDIS_NOTIFICATION_IN_SZ
#define RNDIS_DATA_OUT_PMAADDRESS RNDIS_DATA_IN_PMAADDRESS + RNDIS_DATA_IN_SZ
How will this translate into
HAL_PCDEx_SetRxFiFo and HAL_PCDEx_SetTxFiFo calls ??
Thanks in advance
2018-12-12 01:20 PM
> from STM32F4
Which 'F4?
The Device-only USB generally sets FIFOs as byte-addresses, while the FIFO settings in the OTG_USB are in 32-bit words.
Read the comments I wrote above. I don't use Cube/HAL.
JW
2018-12-13 12:15 AM
I'm trying to port
https://github.com/fetisov/lrndis
to a STM32F746G-Discovery board
I will look in to your answer more deeply
Thanks
2021-08-27 01:17 AM
As above configure, only display "Serial Port Com", can not display "RNDIS ethernet" ? So what is the problem?