How does Ethernet RX descriptor wrapping work on STM32H7?

PWint · ‎2020-08-05

My Ethernet driver is not wrapping as I expect.

Section "61.10.1 Descriptor Overview" in RM0399 states that descriptors up to N-1 is owned by the DMA and the DMA continues to process descriptors until the Current Descriptor Pointer == Tail Pointer.

In order to exit suspend state, the tail pointer must be updated so that the Current Descriptor Pointer < Tail Pointer.

Using the example in Figure 841, the tail pointer points to entry 10 (which is not a valid entry since only 0 to 9 are valid). I can see that the DMA runs until the current descriptor points to 10, but it does not wrap back to zero. If the tail pointer must be larger than the current pointer, what should it be? Should it point to entry 11??

When will the DMA wrap, and start operating on buffer 0 again?

MWB_CHa · ‎2022-04-04

Hello @Pavel A. ,

Sorry for the delayed answer.

We confirm this issue was present in the legacy ETH HAL driver (alignment on 512 bytes).

But this problem was fixed in the new ETH HAL and now Rx Buffers are allocated from LwIP stack memory heap, then passed to ETH HAL driver (__ALIGNED(32)).

Kind Regards,

Pavel A. · ‎2022-04-04

Dear Chekib, thank you for the update. Good to know.

Piranha · ‎2022-04-04

> We confirm this issue was present in the legacy ETH HAL driver (alignment on 512 bytes).

Just to be sure... What was the exact reason for this issue? Just a short hint and/or Github link that shows the respective code with the issue would be nice.

MWB_CHa · ‎2022-04-05

Hi @Piranha ,

The problem is not located in a specific code section, it is a structural problem due to passing the descriptor to the DMA before it is freed by the application.

I hope it helps ?

Kind Regards,

Piranha · ‎2022-04-16

I know that problem (flawed API by design because of absolute incompetence...), but I don't see how it relates to some specific buffer alignment.