> Apart from the pull-ups value can you estimate difference and disadvantages of sending more than 9 clock pulses at the beginning of the transmission?
The idea behind this is, that if SDA is blocked, that's a slave amidst a read (i.e. slave transmits) - and 9 pulses should ensure the slave transmits the whole byte and then sees a NACK from the released SDA, which results it stop the read. However, there are various deviant I2C slave implementations, as well as situations like slave is amidst an ACK to write (in which case blindly issuing 9 pulses will bring it to just another ACK), and various situations resulting in faulty behaviour of multiple devices on the bus.
So the real goal here should be to achieve free bus (i.e. both SDA and SCL high), and then issue a STOP, upon which all conforming slaves should reset their internal state machine. Assuming relatively sane slaves, this may happen sooner than but not later than in 9 pulses, so the correct description is, issue up to 9 pulses, and as soon as the bus is free, issue a STOP.
If SCL is blocked (and it's not temporary due to slave stretching clock), all chances are off and the only way to release bus is to reset the slaves, either through reset pin provided they have one, or through power cycle.
> As a workaround we are toggling PE bit to 0 and back to 1 if we detect transmission error and BUSY flag is still set after transmission. Is any disadvantages could be caused by this method?
This and this may be a problem with this in the I2Cv2 (I2Cv1 as in 'F1..'F4 has a different set of issues).
JW
