HAL Ethernet SMI - read more than 31 registers?

[John Doe1]

How can I read more than 31 registers using SMI/ethernet? Microchip(.com) LAN ic allows read many more register (at custom address, like 1BCh).

I tried to use HAL_ETH_ReadPHYRegister(), but

• PADDR: the PHY address is 5 bits, allowing 32 unique PHY addresses. The MSB bit of
the address is the first transmitted and received.
• RADDR: the register address is 5 bits, allowing 32 individual registers to be addressed
within the selected PHY device. The MSB bit of the address is the first transmitted and
received.

[waclawek.jan]

Registers beyond the standard 0x1F are accessed through some extended mechanism, usually either indirect access using one standard register as address register and one other as the indirect data register; or through paging. MCHP now has through acquisitions 3 different ETH PHY lines at hand, so specifics depend on the particular chip and are detailed in that chip's datasheet or other accompanying documentation.

I don't Cube, but this is more about understanding the underlying mechanism.

JW