HAL bug: HAL_TIM_PWM_Stop() function stops timer even when another channel is configured for input capture?

[RAltm]

Hi,

I'm on a L011 device with the following configuration for timer 2:

Channel 1 is in input capture mode, rising edge. The timer itself is in auto-reset mode, on each rising edge on channel 1 the timer count is copied to the CCrx register and the timer itself is reset. This is to measure the duration between edges.

Now, depending on the measured pulse width, I want to output a defined pulse width with channel 2 of timer 2 (the same timer). There's also the case where no pulse has to be generated at all.

I couldn't get this working with output compare mode since I found no way to reset the OCxREF flag, so I configured the channel to PWM output mode. My idea was to output the pulse by simply starting or stopping the PWM channel by corresponding HAL functions HAL_TIM_PWM_Start() / HAL_TIM_PWM_Stop(). Now, it seems that the stop function disables the timer (clearing CEN flag) if no other output(!) is active, the enabled input compare on channel 1 is ignored. I'd say this is a bug in HAL, the timer shouldn't be stopped if a channel is active in any mode, not only output enabled.

Aside from bug or no bug, does anyone have a suggestion how I can realize the above mentioned pulse without stopping the timer?

Regards

[Bob S]

Putting aside for a moment the issue of HAL disabling the entire timer...

I don't think this can work. You have two sources resetting the timer counter register: rising edge on channel 1, and the end of the PWM period from channel 2. And depending on your PWM settings, a short pulse period on channel 1 may interfere with your PWM output. You are going to need 2 timers for this.

Now, going back to the HAL question: HAL presumes that each timer is performing only one function. In fact, based on the STM32L4xx HAL code, it appears the HAL_TIM_PWM_Start/Stop functions presume that you are only using one channel of PWM. If you have 2 PWM outputs from the same timer (must have the same period but can have different duty cycles), calling HAL_TIM_PWM_Stop() on one channel will halt both. So the answer here, *IF* you ever find a way to do both of your functions with one timer, is to bypass HAL for enabling/disabling the PWM.

[RAltm]

Hi Bob,

thank you for your answer.

For the HAL issue, it seems it was my fault: I accidentally disabled the input channel before calling HAL_TIM_PWM_Stop(), so the HAL saw only one channel and then disabled the timer.

For the pulse measurement/generation, why should the timer be reset by the CC event from channel 2? As far as I understood the timer in reset mode, with selected TI1FP1 as trigger source, the reset should only depend on channel 1 (input capture).

The pulse length generated on channel 2 is shorter than the expected time between the edges on the input channel, so this should not be an issue. However, I agree that I should implement some fault management if there are glitches on the input channel.

Regards

[Bob S]

Yeah, I didn't look at the __HAL_TIM_DISABLE macro close enough. It only disables the timer if all timer channels are disabled.

As for resetting the counter. Honestly, I am not sure what will happen. What I do know is that PWM mode attempts to reset the CNT register when it matches the time channel's CCR register (i.e. the PWM period). That is how PWM works. The diagrams don't show enough detail to know how the hardware deals with being told to reset the CNT register from 2 different sources. Does slave "reset mode" take priority (and override) PWM mode? Or does PWM mode take priority over slave reset mode? Or does the hardware allow BOTH sources to reset the CNT register. You may just have to experiment and see. Set your input pulse to a longer period than your PWM output and see if (1) you get the pwm that you expect and (2) you get the correct input capture value for the period of your input signal.

[RAltm]

Hi Bob,

What I do know is that PWM mode attempts to reset the CNT register when it matches the time channel's CCR register (i.e. the PWM period). That is how PWM works.

I think you mean the ARR register? :grinning_face:

When CNT reaches ARR, then CNT is reset (assuming upcounting mode). Reaching CCRx register toggles the output.

[Bob S]

You are right. And I'm crawling back into my hole. Apparently this isn't my day for paying attention to details :)

[RAltm]

I know what you mean :>