H743IIT6 USB DMA and Dcache working together produce anomalies

[andy817501]

• stm32h743iit6
• threadx + usbx
• use USB_OTG_HS as CDC host ,
• USB_OTG_HS dma_enable = ENABLE and enable the dcache
• vscode gcc13.2.0

when i used the usb_host and opened the dma and dcache, the usb cannot work I have divided the memory area used by USB DMA into RAM-D2,I have configured R2 MPU_ACCESS_NOT_BUFFERABLE ， MPU_ACCESS_NOT_CACHEABLE ， MPU_ACCESS_NOT_SHAREABLE and
MPU_TEX_LEVEL1 and when I turn off DCAHCE, USB host and dma can be used normally,or I can use SCB->CACR |= SCB_CACR_FORCEWT_Msk And use __DSB() in the HAL_SCD_ShenfyURBChange_Callback function; It can also be used, but I'm not sure if it will affect performance. Is there any way not to turn off dcache and not to use SCB->CACR |= SCB_CACR_FORCEWT_Msk for dcache.

But I use USB_OTG_FS dma enable=ENABLE and turn on dcache to make it work as a cdc device, It can work normally,I don't need to turn off dcache or use SCB->CACR |= SCB_CACR_FORCEWT_Msk, but usb_host can not work , i find when i open the dcache and dma in usb host I do get 2-5 trasnfers through, and then it stalls.

[andy817501 · Accepted solution]

I have continued to address the byte alignment issue regarding DMA

[FBL]

Hi @andy817501 

Since the USB DMA and cache might not be coherent, you need to ensure that cache lines are properly invalidated before DMA reads and flushed after DMA writes.

To do so, invalidate DCache before DMA Read:

SCB_InvalidateDCache_by_Addr((uint32_t*)buffer, size);

Then, clean DCache after DMA Write:

SCB_CleanDCache_by_Addr((uint32_t*)buffer, size);

Would you mind sharing your workaround? 

[andy817501]

I understand what you mean, but I have already used no dcache in the memory area of DMA on USB , I don't need to use  invalidate DCache before DMA Read , In my previous description, I have clearly described the MPU configuration of Ram-D2 , And the same MPU configuration,for Ux_Device_CDC_ACM , I Can use the dache + dma work together , But for Ux_Host_CDC_ACM i can not ,This is where I am confused, looking forward to your reply.