Does the DMA Arbiter allow round robin preemption after each piece of data to keep multiple peripherals going at once or does the DMA controller completely block until an entire block of data has finished transmitting?

[MFolk.1]

I am working with the STM32L4S9AII6 MCU on a project where I am being asked to replace an FPGA implementation with this CPU. We are maxing out all 14 DMA streams via SPIs, I2Cs, & UART. As you can imagine, I am working with some serious hard real-time deadlines. I am using FreeRTOS.

I think this is a confusing topic to discuss over a forum, so let me use an example to pose my question. Lets say I have 2 SPI peripherals configured. We'll call them SPI1 & SPI2. Both transmit at say 10MHz or whatever. Both are configured to transmit in 8 bits (1 byte) at a time. Both NSS lines are controlled through software to allow this enable line to be pulled low for the entire duration of a block transfer (multiple bytes per DMA request). Now lets say SPI1 attempts to transmit a block of 8 bytes. Immediately after, SPI2 also attempts to transmit a block of 8 bytes.

Question:

Does the DMA engine block on SPI1 until SPI1 has finished transmitting all 8 bytes and then allow SPI2 to begin transmitting its first byte?

-OR-

Does the DMA engine block only while it is retrieving completed/buffered data (1 byte at a time) from SPI1 followed by requesting then next byte if needed? Then the DMA Arbiter would have the opportunity to use the time between SPI1 bytes to initiate transfer on SPI2.

My point being that why should the DMA have to block on a peripheral when it isn't the entity responsible for transmitting the data. In my mind, the DMA should only have to block long enough to keep each peripheral busy and should therefore be able to keep multiple peripherals busy at once.

In other words, can the DMA allow parallel transmission of peripherals?

[TDK · Accepted solution]

The DMA can service multiple things "at once", and only transfers data when there is a request. It will service SPI2 if no pending SPI1 requests are made. Technically it only does one at a time, but there is no waiting on things to flag a request.

However, the L4+ has a SPI TXFIFO which can hold multiple bytes at once. Depending on your setting, there will be multiple SPI1 requests made in order to fill up the 32-bit buffer before SPI2 requests are serviced.

In practice, only the SPI may start taxing the resources here, but only at max data rates. At 10 MHz, a requests a ~1MHz each is very doable on two peripherals at once. UART and I2C are slow.

[waclawek.jan]

Also, read AN2548.

JW