2019-11-13 12:45 PM
Hi, in all the example code I've found related to using FreeRTOS and LwIP and performing Ethernet related tasks the MPU is always used to protect the Ethernet DMA. Why is this the case and what could go wrong if the MPU is not used?
Thanks,
Doug
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2019-11-14 10:42 AM
The short answer - no.
But there are useful benefits of using MPU. Typically it's used for two purposes:
You can find more details on this in AN4838 and AN4839. And also AN4667 and AN4891 are useful. Memory caching obviously is related only to Cortex-M7. As for a memory types...
The Cortex-M processors never perform memory accesses out of order compared to instruction flow, however, the architecture does not prohibit this in future implementations. ARMv7-M code written to be portable to ARMv7-AR processors, like Cortex-A9, must already take account of this ordering model.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHJIIIC.html
But take a note that Cortex-M7 is not included in that AN321 and... Here we go - Cortex-M7 is that future implementation they were talking about and it really is reordering memory accesses.
2019-11-13 04:31 PM
The code like this ? It does not protect the DMA. It sets the correct attributes on memory areas shared with the ethernet controller over DMA.
This saves the programmer from flushing and invalidating the cache all the time.
-- pa
2019-11-14 06:41 AM
Yes, that's the demo code I'm talking about. Ok, thanks for the info.
2019-11-14 10:42 AM
The short answer - no.
But there are useful benefits of using MPU. Typically it's used for two purposes:
You can find more details on this in AN4838 and AN4839. And also AN4667 and AN4891 are useful. Memory caching obviously is related only to Cortex-M7. As for a memory types...
The Cortex-M processors never perform memory accesses out of order compared to instruction flow, however, the architecture does not prohibit this in future implementations. ARMv7-M code written to be portable to ARMv7-AR processors, like Cortex-A9, must already take account of this ordering model.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHJIIIC.html
But take a note that Cortex-M7 is not included in that AN321 and... Here we go - Cortex-M7 is that future implementation they were talking about and it really is reordering memory accesses.
2019-11-14 10:47 AM
Thanks for that info. For now I'm keeping my ethernet implementation as similar to the example code as possible so will also use the MPU as used in these examples. I've seen some of the posts you've made about ethernet driver issues in the code provided by ST, are there any specific changes you've made to this that you feel are critically important to achieve best results?