Hi, my company is pursuing a UL1998 (very similar to IEC 60730-1) Functional Safety Certification. In reading the ST Application Note (AN4435) I see in section 3.3 SRAM Tests, it says "Some ST Microcontrollers feature a built-in word protection with single-bit redundancy (hardware parity check) applied on CCM RAM or at least on a part of the SRAM."
On our current project, we are using an STM32F429ZI MCU and I see it has 64kB of CCM, but am having trouble finding documentation for its use. In a handful of forums, I have seen them discuss how CCM is only accessible by the CPU (rather than also by DMA), but I cannot find anywhere else alluding to it having a built-in hardware parity check. I wanted to see if someone could point me to documentation on this or at least confirm that the CCM in the STM32F429ZI does have the hardware parity check, and if so, what happens if the hardware parity check fails on startup or during runtime.
