Bug in STM32L151 (and others) driver code - These chips don't have a BRR register.

[jfolsom]

The STM32L100/151/152/162 Reference Manual says that there is a BRR (bit reset register) for Category 3 devices, when, in fact, there isn't. This is a known problem, please see:

https://community.st.com/s/question/0D50X00009XkWybSAF/brr-register-does-not-work-for-stm32l100rc-and-stm32l152rc-boards

and

https://community.st.com/s/question/0D50X0000APZncVSQT/stm32l151rc-gpio-brr-register-missing

But in addition to the documentation error, the driver code also doesn't work because it tries to access this non-existent register to clear GPIO bits. This from the stm32l1xx_ll_gpio.h code generated by STM32Cube MCU Package for STM32L1 Series, v1.8.1, starting on line 934:

__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
#if defined(GPIO_BRR_BR_0)
  WRITE_REG(GPIOx->BRR, PinMask);
#else
  WRITE_REG(GPIOx->BSRR, (PinMask << 16));
#endif /* GPIO_BRR_BR_0 */
}

A user can fix the issue by simply using the BSRR register instead of the BRR register. (commenting or deleting lines 3, 4, 5, and 7 above).

But ST should go in and remove the BRR entry from the GPIO_TypeDef struct and the bit definitions (e.g. GPIO_BRR_BR_?) from all the Category 3 devices' header files (e.g. stm32l151xc.h, etc)

[Imen.D · Accepted solution]

Hello,

You are the right, I rasied this issue internally for fix in the coming release of STM32CubeL1 firmware package and aligned with the reference manual.

Note that the reference manual RM0038 will be modified in chapter: "7.4.11 GPIO bit reset register (GPIOx_BRR) (x = A..H)":

- Remove "Cat.3" from description. So final sentence should be:  These registers are available on Cat.4, Cat.5 and Cat.6 products only.

Regards,

Imen

[jfolsom]

Thank you Imen,

I saw (elsewhere) that the manual was to be updated, but I wanted to make sure the code was, too :)

Also, hopefully this post helps somebody...

-Jon