STM32H7A3 unusable for VGA

[PMath.4]

Getting stable V-sync and H-sync pulses is critical for clean VGA output. Getting these completely stable on the H743 was difficult and required multiple iterations of different PLL settings. but was possible.

On the Nucleo-H7A3ZIQ it has proved completely impossible.

V-sync pulses are showing a variability of up to 25uS one to the next. This shouldn't be an issue with displays that use a pixel clock but VGA displays don't and are compromised by the variability in timings of H-Sync and V-Sync.

Pity, the 1Mb of internal ram on the H7A3 is enough for a 16-bit 800x600 display without needing external memory but the chip simply isn't usable for this application. :sleepy_face:

[Tesla DeLorean]

It would perhaps help to understand the problem if we knew how you were generating the signals. Via TIMs or LTDC ?

[PMath.4]

Sorry - standard LTDC into R2R DACs, exactly like I have running on the H743. Nothing else active on the processor, no updates to the RAM, framebuffer at 0x24000000

[Tesla DeLorean]

Mouser supposed to have stock shortly, placed some on order.

[waclawek.jan]

Please quantify the jitter you observe. Please output the primary clock source and observe its jitter, as well as the other PLL outputs'.

Please post a minimal but complete compilable example, so that others could reproduce the problem.

What's your primary clock source?

Is this a SMPS-supplied STM32 model?

JW

[PMath.4 · Accepted solution]

Thanks to Jan for pointing at the obvious - which wasn't.

Well it transpires that everything about the Nucleo-H7A3ZI-Q is jittery. Both the output from the onboard ST-LINK V3 (STM32F723) and the internal HSI RC oscillator. And, of course, in both case the jitter feeds through to the LTDC clocks.

I've solved the problem by using an external crystal oscillator chip (EPSON Q3204DC21044200) and now the LTDC output is rock solid.

This is something I haven't seen on other Nucleo boards and isn't helpful!

The ST-LINK V3 clock is crystal derived but there must be something wrong with the electrical design of the layout on this Nucleo version. My other Nucleo boards are ST-LINK V2 and don't have this issue.

For reference the ST-LINK clock jitter is up to 6uS in 16mS and the HSI jitter just slightly less

[waclawek.jan]

> The ST-LINK V3 clock is crystal derived but there must be something wrong with the electrical design

No. The MCO from STLink-V3 comes from HSI.

https://community.st.com/s/question/0D50X0000BiD6fISQS/stlink-provides-808-mhz-instead-of-8000-on-new-nucleoh743zi2

JW

[PMath.4]

WTF?

[Tesla DeLorean]

I'm totally with you there...

[Mikhail Z]

What did you find to be the most stable PLL settings on H743?