Problem with high speed in a custom board with STM32H735IGT6

[JVale.2]

Hi.

I am Jose Manuel. We have developed a custom board where the MCU is STM32H735IGT6, the external SRAM is APS12808L-3OBMX-BA and the external flash is W25Q128JVEIM.

The problem is that we want to work with 100 MHz, but it does not work, it just work up to 60 MHz.

We have developed a board with four levels, the same lenghts in the route and the same vias. Below, attached the interface between the SRAM and MCU. Could you please tell us what steps we have not done? Whats the recommendation to follow?

Thanks you and Best regards,

José Manuel

[AScha.3]

Hi,

i just can say, what i would do :

- leave away the funny and very professional looking meandering lines ( hey, signal speed is about 200mm/ns , so if your traces are +/- 20mm different lenght, you get +/- 100ps delays . at 10ns clock 1% error..just forget it.) so useless here.

- decoupling caps close to chip + via to power (you already have it, i think)

- in blue layer (bottom ?) almost free space, so try to do the traces short (avoid this big loop areas, you have now on some (this pick up fields and emit emv... :) ), try to bring them close together to form a bundle between cpu and ram. (but not too close, to avoid to much capacitive coupling ! about 1mm distance, if possible)

- the damping resistors could be 33...150r , i would start with 75 ohm , in all traces same value.

- position of this resistors is not important (you anyway never get a "correct" transmission line, this would need termination impedance on both (!) ends - forget this here); position need not to be close to chip/pin; just (without resistors )try to find direct , short and bundled traces from cpu to ram and then insert the damping resistors, where you have room and not generate useless loops and deteriorating bypass loops.

+ show your design, if you want some checking , before production ...

[Piranha]

Generally the most important factor is not to make a 50R impedance, but to match the same impedance from the source to the destination and in between. The lesser the points, where the impedance is changing, the better. The series resistors have to be added at the source (output) so that the output driver's and resistor's impedance added together matches the chosen target impedance. On bidirectional pins generally one must put the series resistors on both ends and match them with the respective output drivers. Some chips for some interfaces can have an output drivers, which are already matched for some specific impedance and therefore doesn't need an additional resistors for that particular impedance. Also on some denser and/or cheaper boards ST omits the resistors on the MCU end because STM32 microcontrollers have a drive strength configuration for outputs and that partially solves the impedance matching issues.

As ST mostly uses 33R resistors and targets for 50R impedance, one can assume the output driver's impedance as 17R. Therefore, if your current actual PCB design impedance is closer to 39R, then just use 22R resistors for this design.

But take a note that, for example, USB and Ethernet interfaces require 90R and 100R differential impedances. That is a requirement for the external signals of the PHYs, connectors and wires, not the internal CMOS level and other signals, of course. Therefore for such interfaces one cannot choose any impedance, but has to adhere to the standard.

And, if it's impossible to match the impedance properly, it becomes even more important to make those wrong routes as short as possible.

[Sco]

Hello 

From hardware point of view:

1. the equal length of the signals are very important = > resistance matching(here should be 50ohm).

2. another important point is that you need to make sure the reference GND, in your picture, can't see the GND layer directly, are layer 2, layer 3 with good GND here(as a reference for the signals).

3. when you talk about the resistor on board, the resistors should be near the source side(MCU).

[JVale.2]

Hello,

1. The length of the signals are equal, approximately 51 mm. Our possible failure is the impedance, so we will modify the widht of the signals.

2. Layer 1 is TOP (red), layer 2 is GND, layer 3 is PWR (3.3V), layer 4 is BOTTOM (blue). According to the AN4661 document (section 8.4.3), we should put 10nF capacitor, but... how? where?

3. On the evaluation kit (STM32H735IG-DK), the resistors are close to the SRAM.  So is it a other possible failure? Can we solve it moving the resistor to the outside of the MCU?

Thanks you.

[LCE]

2. 10nF capacitor:

Best would be to put a few of these at source and destination, and close to the vias where the high speed signals change layer. Think of the caps as the helping the signal GND return path via the VCC plane.

I prefer GND planes only, if not enough layers are available maybe I would use a GND plane for some power supply lines, but only if these would not cross any critical signals on the next layer.

But even with GND planes only, put a few stitching vias (GND to GND) close to the vias where the signals change layers.

[Sco]

1. Regarding the resistance matching, it depends on the width of the signals, the stack, the process of PCB manufacturing company. I can't judges if the width is ok or not, I suggest you to communicate with PCB manufacturing company: make it clear that you request them to do the resistance matching with 50ohm(refer to L2/L3), they will adapt the width and back to you with an EQ file. You can communicate until you get what you want.

2. Always for each power, there should be a/several bypass caps(to GND) with value 100nf, 1uf... as described in the document(AN4661 section 8.4.3), it recommends 10nF, it means the Power which these signals(memory) refer to, for such power, there should be a 10nF cap to GND.

3. For this point, it's better to place these resistors close to the MCUs, but I can't judge it's this point that casues the failure. I recommend you to check the shcematic and layout carefully besides this point.

[Alex - APMemory]

Is you issue about Flash or RAM?

Alex

[Tesla DeLorean]

Good question, but the word "RAM" with respect to the interface and the problem is used multiple times.

[JVale.2 · Accepted solution]

Hi everyone,

We have redesigned the board trying to set the impedance of the lines to 50 ohms and followed the steps in document AN4661 (section 8.4.3). The result has improved, we can work up to 120 MHz.

Thanks for your helps.

José Manuel

[Alex - APMemory]

Thanks for the confirmation and good to hear

Alex