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NUCLEO-H723ZG (ADC DMA TIM2 LWIP UDP)

AntoR
Associate III

 

 

I am doing research to test the performance of an MCU based system that transports the raw PCM samples of the STM32H723ZG ADC via Ethernet, LWIP in UDP.
the ADC is set to 8 bits of single resolution, and I have set the TIM2 timer to drive the ADC clock at 8Khz. on the Host side, I have a Python application that listens on port 8090 and when it receives the samples in UDP it redirects them to the speakers. The ADC offset was made with a resistive divider of 2 10Kohm resistors to have 3v3/2 = 1.65v.

On the host side when the samples arrive, the audio signal, although with background noise that I believe to be normal since I have not yet implemented any type of filter, is as if it arrives undersampled. Basically if I inject an audio signal higher than 400Hz, the host listens to it as if there was aliasing, when with a sampling of 8khz I should not have problems up to about 3/4 khz.

below is the code if someone helps me understand what I'm doing wrong.

the

TIM2 PSC = 0 ARR = 244  clock is 250Mhz

and  ADC DMA SAMPLE BUFFER size is 64

sample rate will be 250000khz/244/64 = 16/2 = 8Khz   (if correct)

 

for launch python program on debian machine 

python3 udp_pcm_listner.py 0.0.0.0 8090| aplay -r 8000 -f u8 -

 

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