I'm new to STM32 and designing my first STM32F446RE-64 pin PCB. For reference and education, I'm using the Nucleo-64 STM32F446 board, the STMF4 datasheet and the STMF4 getting started with MCU hardware development guide. I have the following questions about decoupling recommendations:
- VDDA
- The reference guide states that the "VDDA pin must be connected to two external decoupling capacitors (100 nF Ceramic + 1 µF Tantalum or Ceramic)."
- The data sheet, unless I'm misinterpreting, seems to show under "General PCB design guidelines" in Figure 47, a decoupling capacitor of size "1 uF // 10 nF" Is this saying 1uF in parallel with 10 nF? Pretty close to the reference guide, but a little different
- Finally, the Nucleo board just seems to have one decoupling capacitor with 100 nF
Is there a reason why the Nucleo board is not following recommendations? Is it because, in place of the high capacitor value, it is using the Ferrite Bead to filter out the low frequency noise?
2. VDD
- Both the PCB and reference manuals seem to recommend N 100 nF capacitors for each VDD/VSS pair + one 4.7-10 uF capacitor for the package.
- The Nucleo board doesn't seem to include the 4.7-10 uF for the package. It does seem to have a 10 uF capacitor where Vin comes into the board, but there are two linear regulators and other components between that cap and the package.
Is there a reason the Nucleo board doesn't include the 4.7-10 uF capacitor near the package? Are the caps around the linear regulators enough to stabilize the signal and filter out the low frequency noise allowing the nucelo boards to leave out the 4.7-10 uF cap for the package? Or, is the recommendation merely for bulk capacitor needs and the 10 uF cap near Vin serves that purpose?
Thank you for the help!
Scott
