MB1440 circuit diagram

[PHolt.1]

Hi All,

Does anyone have the circuit diagram (schematic) for this board?

Basically (and I have posted about this before, without any conclusion) I have several boards which work perfectly (sw download and SWD debug) via the big 20-way CN2, but are unreliable via the little 10-way CN1 (sw download works but SWD always fails within some tens of seconds or minutes).

Buzzing the thing through with a meter, I can verify CN1 and CN2 are interconnected directly, on all the relevant signals, so this difference is a mystery. But maybe CN1 has some funny stuff on it. I see no useful explanation in the PDF

https://www.st.com/resource/en/user_manual/dm00526767-stlinkv3set-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf

It may be that JP4, JP5 and others around there made CN1 different to CN2.

The issue is not affected by whether Cube IDE debug (STLINKV3) is set to 24MHz or 8MHz. SWD is set to 2MHz and reducing that makes no difference to reliability either.

Many thanks in advance.

[Ggvfd.2]

Yes; also with contemporary isolators (the RF primarily based ones, now not vintage-fashion optoisolators) there's no cause for the low velocity when the ISOL board is established. It reduces the rate of STLINK V3 from 24MHz to 8MHz. I did check and it sort of runs as much as approximately 16MHz but no longer reliably.

[Ggvfd.2]

Yes; also with contemporary isolators (the RF primarily based ones, now not vintage-fashion optoisolators) there's no cause for the low velocity when the ISOL board is established. It reduces the rate of STLINK V3 from 24MHz to 8MHz. I did checks and it sort of runs as much as approximately 16MHz but no longer reliably.

[LChis.1]

That ship has already sailed. Somebody has decompiled the Java programmer, found the f/w AES encryption keys, downloaded his own snooper app to the chip and extracted the bootloader, patched it to not burn the read-lock bits... and there are already V3 clones on blogs or Github.