Achieve max timer clock on STM32H7

[icethi]

Hello,

I am trying to achieve the maximum timer clock on the STM32H723ZG for input capturing. In the data sheet is written under Table 4: "The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register."

I tried to achieve this in the Clock Configuration but it seems like the only solution I found is invalid (see screenshot below). Can I still do that? Or is there another way to do that?

I tried to compile it and it worked without a problem. Sadly I cannot test it on hardware due to delivery.

Thanks in advance!

[AScha.3]

Red = wrong !

set HPRE div 2 , then get max. clk on APB1 timer clk.

try.

[icethi]

I tried, HPRE /2,  D2PRE1 /2 (137.5 MHz is max for APB1 Peripheral) and then APB1 Timer is 275 MHz. In the data sheet it is written, that 550 MHz should be possible, but I cannot find a way?

[AScha.3]

look in clock tree (i dont use H723 , so would need to download and make new project...)

there could be a separate clock mux for TIMx , like this :

of course you have to activate/enable the timer , otherwise its grey (disabled).

[AScha.3]

btw

in my ds H723 :

where is 550MHz written ?

[icethi]

In the datasheet: https://www.st.com/resource/en/datasheet/stm32h723zg.pdf
On page 41

[STTwo-32]

Hello @icethi 

As indicated on the table, 4 of the datasheet, the maximum timers clock is 275MHz. But the Systick timer clock is up to 550MHz. The answer of this post may help you.

Best Regards.

STTwo-32 

[icethi]

But the systick clock is different from the timer clock, right? According to the data sheet the timer clock should have 550 MHz.

[Tesla DeLorean · Accepted solution]

What would HELP, is that the Foot Note on Table 4 NOT BE THERE if none of the TIM listed in SAID TABLE support 550 MHz

SYSTICK, nor HRTIM, are in that table, and Tilen's post is from SEVEN years ago, for a different processor/die

Fixing the documentation needs to be JOB#1, there's just way too much of this cut-n-paste nonsense that dwells for years. Need to hire some technical writers and proof-readers.

For counting elapsed machine cycles, perhaps look at DWT CYCCNT

Fantastically UNHELPFUL

[AScha.3]

See it as marketing gag : there is one timer, sys , that can run on core clk , 550M . All other NOT .

Except you set the D2PRE1 yourself ... overclocking . The timer should work at 550M...but what else works, or not, you have to test yourself.

I overclocked some cpu, just for fun , ie. F303 72M max, works also at 128M ; pi-pico (M0+ core) 133M , works up to 300M ! 

But the question is : do it for fun, or test , or expect reliable working at all temperatures etc.