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icethi · 2024-02-13

Hello,I am trying to achieve the maximum timer clock on the STM32H723ZG for input capturing. In the data sheet is written under Table 4: "The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits i...

icethi · 2024-02-13

But the systick clock is different from the timer clock, right? According to the data sheet the timer clock should have 550 MHz.

icethi · 2024-02-13

In the datasheet: https://www.st.com/resource/en/datasheet/stm32h723zg.pdfOn page 41

icethi · 2024-02-13

I tried, HPRE /2, D2PRE1 /2 (137.5 MHz is max for APB1 Peripheral) and then APB1 Timer is 275 MHz. In the data sheet it is written, that 550 MHz should be possible, but I cannot find a way?

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