L6599AT Questions Q1: STBY pin does not stop pulses on gate drive outputs. Q2: Datasheet confusion for: (a) Soft-Start, (b) LINE.

[FBaro.11]

Question 1:

In our circuit Pin 5 STBY is pulled down to 0V to instantly stop pulses on gate drives. But sometimes when STBY=0V we still see pulses at the gate driver outputs LVG, HVG. The datasheet does not mention that gate pulses may still happen.

I have noticed a similar question here:

https://community.st.com/s/question/0D50X0000AuqowSSQQ/how-to-disable-l6599-output

The answer to that question from Central Support suggests that using Pin 5 STBY is not a reliable way to stop gate drive. So then: what is the **best** way to immediately turn off both gate drivers? However, please note that we do **not** want to latch the L6599 off since this would require a power-cycle on VCC to restore gate drive pulses (eg: pin 8 DISABLE is not suitable, since it latches the chip OFF and requires VCC to go below ULVO level to re-start the chip. We simply want to shut-down & allow the re-start of gate-drive with a control logic signal. Our circuit schematic is below, to stop gate drive the STBY (pin 5) is being pulled down to 0V by V7, this has been confirmed with scope probe on V7 drain (X47).

 

Question 2A:

The datasheet description of (a) Soft Start is confusing.

The description of Pin 1 on page 5 says:

[start of copy]

Soft-start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns off (Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5V, DELAY > 2 V) to make sure it is soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75 V.

[end of copy]

Question: Why is ISEN mentioned twice at 2 different voltage thresholds? If the internal switch discharges Css if ISEN > 0.8, then it will also discharge it when ISEN > 1.5V. Why is 1.5V mentioned?

Question 2B:

The datasheet description of (b) pin 7 LINE is also confusing.

The description of Pin 7 on page 6 says:

[start of copy]

Line sensing input. The pin is to be connected to the high voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.24 V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC operation is re-enabled (soft-started) as the voltage exceeds 1.24 V. The comparator is provided with current hysteresis: an internal 13 μA current generator is ON as long as the voltage applied at the pin is below 1.24 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal Zener diode. Activating the Zener diode causes the IC to shut down (not latched). Bias the pin between 1.24 and 6 V if the function is not used.

[end of copy]

So what I can tell from this description is that when the voltage at pin 7 goes outside the range of [1.24V to 7V] the IC will shut down but not latched. What is not clear is how the IC restarts from this shutdown when the voltage returns to this range.

If it returns from the low end, then we are told that Css was shorted, and so when Pin 7 returns above +1.24V, the IC will restart with Soft-Start initiated.

If it returns from the high end, we are not advised about the status of Css. When Pin 7 returns below 7V, is soft-start also initiated?

There are other questions about LINE function:

1. What is the time-delay from when this pin is activated (below 1.24V, or above 7V) to when the gate pulse is turned off? Is this delay different between these two activations?
2. For activation by >7V, how much hysteresis is in the threshold to cause the device to re-start?
3. What is the time-delay from when this pin returns under the activation threshold, to when the first gate drive pulse occurs?
4. What is the switching frequency at the time the gate drive pulses restart?
5. Which gate goes HIGH first, LVG or HVG?

Update 26-Apr-2021: there is a related earlier question (June-2017), but it seems I cannot see the answer to it. Here is the link to that question:

https://community.st.com/s/question/0D50X00009XkXdHSAV/using-l6599-stby-pin-for-power-output-control-through-pwm

[Cristiana SCARAMEL]

Hello @FBaro.1​,

I was able to reach out to product experts to help you ;)

Question 1

The pin STBY stops immediately the gate drivers, there is only a condition that could override the STBY signal: if the Css pin voltage is < 3V the STBY pin voltage is ignored. Therefore I suggest to double check that during normal operation the Css voltage is 2 V, as it should be after the soft start end.

The STBY is not intended to be used to stop the operation of the L6599A because this pin is designed to managed the burst mode of the converter, thus when the pin is released the converter restarts without any soft start, and this can be a dangerous transition for the converter.

To stop L6599A operation and restart operation safely it is recommended to pull down the LINE pin, it stops the L6599A and discharge the Css capacitor; in this way at next restart the converter will be soft started.

Question 2A

Because the Css is partially discharged only for the time needed to Css to drop from 0.8V to 0.75 V, and this is the overload protection, limiting the o/p power. Meantime the Delay capacitor is charged; once it reaches 2 V the soft-start capacitor is completely discharged so that the switching frequency is pushed to its maximum value. As the voltage on the pin exceeds 3.5 V the IC stops switching, then as the voltage drops below 0.3 V it restarts via a soft start cycle.

In case of dead shorts, the current is totally out of control and current rises quickly; once the ISEN reaches 1.5V the IC latches and it is necessary to recycle the Vcc to resume operation

Question 2B

LINE pin is dedicated to enable the L6599A if input voltage level is correct and prevent mis-operations if it is out of range. The 1.24 V threshold has an hysteresis and IC is soft started. 7V threshold has no hysteresis. There are no internal programmed delays on this pin, just logic propagation delays. Switching frequency at restart depends by the total current is tied by the RFmin pin.

I hope this post can help you.

[FBaro.11]

Hello Cristiana,

thank you for your detailed response. I have a question about your answer under Question 1.

You wrote: "if the Css pin voltage is < 3V the STBY pin voltage is ignored. "

Is the "< 3V" a typo - did you mean, perhaps, "< 0.3V" ?

I have other comments regarding the other responses, but perhaps it is best to deal with this one first, to prevent any further confusion.

[Cristiana SCARAMEL]

Hello @FBaro.1​ ,

Yes, it is typo.

The correct number is <0.3V, thus the correct statement is: “if the Css pin voltage is < 0.3V the STBY pin voltage is ignored.