L6599AT gate drive pulses appear unexpectedly

FBaro.11 · ‎2021-04-22

We noticed that there are pulses at the gate drive outputs (pins 15 HVG, & 11 LVG) during the ramp-up of the control voltage (pin 12 VCC).

This is what we saw: when VCC reaches about 11V, a sequence of pulses appear on both LVG and HVG. First LVG went high (VCC) for a long period of about 10 micro-seconds, then it went low, and after a delay of about 300ns, 3 narrow pulses (each less than 250ns wide) appeared alternately on both HVG and LVG, in normal sequence with deadtime of about 300ns, starting with HVG first, and the last pulse on LVG. Then the pulses stop for a very long period (many hundreds of milli-seconds), and then they start again in accordance with the normal function of the controller in response to voltages at the control pins. The behaviour occurred regardless of the rate of rise of VCC, we varied this from very fast (2 milli-seconds rise from 0V to +12V) to quite slow (100ms from 0V to +12V) and each time the response was the same.

We also saw pulses on the timing cap, pin 3 CF. This voltage was held at 0V during VCC ramp, then held at about 0.5V for the first pulse (LVG high for 10us), then it showed the usual triangle waveform for 3 peaks and 3 valleys during the narrow pules on LVG & HVG, then it returned back to 0V.

During the time of these unexpected pulses (during the ramp of VCC) all of the inputs are set to voltages that would normally cause gate drivers to both stay at 0V. To be specific, these are the voltages at the control pins during the ramp-up time of VCC and during the time when these pulses occur:

Pin 2 TripDelay is at 0V.

Pin 5 STBY is at 0V.

Pin 6 ISEN is at 0V.

Pin 8 Disable is at 0V.

Pin 4 is at 2V (as expected). Note that the current out of this pin is at maximum, since the control voltage is at 0V (refer datasheet figure 22, this is equivalent to the opto Q being fully ON) - this would normally cause the Fs to be a minimum (maximum output power), but at this time the chip is being held in the shutdown state by pin 5 and pin 1 (Soft-start) is at 0V, which should be forcing Fs to be very high.

So to summarise: during VCC ramp up, our circuit keeps the pins of the chip in the states necessary to prevent any pulses appearing on LVG & HVG, yet we are seeing pulses. This leads me to suspect that this behaviour is built into the chip itself, and is beyond our control. But I have not seen any mention of this behaviour in any datasheet, or app note, and I looked in this forum but could not find any mention of it.

I have attached some waveforms that show this.

Please respond to the following questions:

Q1. Is this behaviour normal?

Q2. is any way to prevent these pulses from occurring?

Q3. Does this behaviour occur for all the different variants of this chip?

Q4, Does this behaviour also occur for the new chip, the L6699?

Regards,

-F.Barone.

Scope images below:

CH1 +12VA (Vcc)

CH2 XAB

CH3 pin 4 RFmin

CH4 pin 3 CF

Scope images below:

CH1 same, +12VA (Vcc)

CH2 same XAB

CH3 moved to pin 11 LVG

CH4 moved to pin 15 HVG

Cristiana SCARAMEL · ‎2021-05-02

Hello @FBaro.1,

below the answers to your questions:

Q1: The behavior in the picture is incorrect, but looking at the waveforms it is clear that the L6599A operation is truncated by any event. I suggest to double check the ISEN pin (2nd level threshold) or the DIS pin in detail with storage oscilloscope, when the gate drivers stop switching, in order to exclude any protection intervention that might latch the IC.

Another possibility could be linked to enable: if at startup the IC is kept disabled by pulling low the STBY pin, as explained in previous answer, the gate drivers can work until the Css voltage is <0.3 V. If this is the case, once again we can say that the correct control pin to eneble the L6599A is not the STBY pin but the LINE

Q2: It depends by the origin of the issue, as per the previous answer

Q3: yes, internal logic is same

Q4: yes

Have a nice day!

FBaro.11 · ‎2021-05-05

Hello Cristiana,

thanks for your answers, please refer my responses below:

Q1.

Point A: You wrote: "The behavior in the picture is incorrect, "

My response: are you saying that these gate drive pulses should not exist?

Point B:

I have already checked the pins you mentioned with a scope, please refer to the 3rd paragraph of my original question. Also, from the schematic it is clear that some pins are not connected to any active device (eg: a logic gate, or transistor) that could cause a voltage, they are held in their de-asserted state (low) by pull-down resistors, specifically:

p6 Isen: 100r to 0V.

p2 TripDelay: 1uF & 100k to 0V.

p8 Disable: 1k to 0V.

The only other signals to consider are pin 1 Css, and pin 5 STBY, let's examine each of these now.

Pin 1 Css: Refer the two images below, the one on the right is a zoom-in of the left image. Please refer to the comments within the image.

Pin 5 STBY: Refer the two images below, the one on the right is a zoom-in of the left image. Please refer to the comments within the image.

I trust that the above clearly proves that all pins of the L6599 are being kept at the correct state to stop the L6599 from activating its gate drivers during the ramp-up of the control power (+12V).

Do you agree?

Q2. Noted.

To prevent these gate pulses, which pins need to be treated differently than what is being done now?

Q3: Noted.

Q4: Noted.

Regards,

-F.Barone

Cristiana SCARAMEL · ‎2021-05-19

Hi @FBaro.1,

Looking at the waveforms it is unclear why the IC starts operating, it is difficult to say the reason because it should not do that. To make hypothesis becomes difficult not having the board on workbench.

Anyway, coming to your Q2, the correct way to stop and start the IC properly is controlling the LINE pin. Therefore I suggest to connect the V7 Drain to LINE pin instead of STBY.

I also suggest:

Decrease the R143 (DIS pin) to 100R for better noise immunity
Increase C68 to slow down the soft start, a fast rising could generate some noise. Typically soft start have much longer time constant
Increase C73 at least to 1nF
If HVG/LVG are driving MOSFETs I wonder the PCB layout is made properly, the gate current is not mixed with control circuitry.