i am using the isolated gate driver showcased in the "EVALSTGAP2SiCSC" evaluation module. i need to implement "Specific Dead Time" between the upper FET and lower FET in the half bridge config. How can i achieve this requirement with this gate drive chip?

[Benji]

Query above is straight forward. - Deadtime implementation options for Half Bridge config.

Deadtime is to "wait for one FET to switch off" b4 turning on the other FET in the half bridge. This is to prevent shoot thru for the Power supply via the Half bridge..

[Cristiana SCARAMEL · Accepted solution]

Hello @Benji​ and welcome to the ST Community.

The STGAP2SICS is a single gate driver there is no the possibility to set a dead time (DT).

You can generate the desired DT with the external PWM coming from a MCU and applying them to the input signals of STGAP2SICS.